Patent US3745371A successfully refreshed from Google Patents.
US3745371A
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Shift register using insulated gate field effect transistors
Assignee: Toshiba Corp
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Filing: 1971-08-10
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Granted: 1973-07-10
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Expires: 1991-08-10
Abstract
Abstract A static shift register in which each shift register unit half comprises a main shift gate including a main shift gate section having an input terminal to which preset binary coded signals are applied and a clock gate section having a gate on which clock pulses for shifting from unit to unit are impressed, an inverter connected to the output of the main shift gate section, and an auxiliary shift gate including a shift gate section with its input coupled to the output of the inverter and with its output coupled to the input of the inverter and a clock gate section having a gate on which clock pulses with a phase inverted with respect to that of the first-mentioned clock pulses are impressed. The main and auxiliary shift gate section, the main and auxiliary clock gate section, and the inverter each comprises a complementary pair of insulated gate enhancement type field effect transistors.
Inventors
- 👤 Y Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:58
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; G11C19/28; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; H03K3/00; H03K3/02; H03K3/353
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
282 words
A static shift register formed of a plurality of cascade arranged shift register units, one of two halves of each said shift register unit comprising a main shift gate which includes a main shift gate section having an input to which binary coded signals are applied and a main clock gate section having a gate on which a pair of clock pulses inverted in phase from each other for shifting the data signals stored in said main shift gate section to a succeeding shift gate section are impressed, an inverter having the input connected to said main shift gate section output, and an auxiliary shift gate which includes an auxiliary shift gate section having the input and output connected to the output and input of said inverter and an auxiliary clock gate section having a gate on which clock pulses with inverted phases to those of the paired clock pulses for said main clock gate section are impressed; and the other shift register unit half comprising at least a main shift gate which includes a main shift gate section having an input to which output binary coded signals from said one shift register unit half are applied and a main clock gate section having a gate on which a pair of clock pulses inverted in phase from each other for shifting the data signals stored in said associated main shift gate section to a succeeding shift gate section are impressed, the improvement being that said both main shift gate sections, said both main clock gate sections, said inverter, said auxiliary shift gate section and said auxiliary clock gate section each comprise a complementary pair of insulated gate enhancement type field effect transistors.
Claim 2
Dependent Claim
282 words
A static shift register formed of a plurality of cascade arranged shift register units, one of two halves of each said shift register unit comprising a main shift gate which includes a main shift gate section having an input to which binary coded signals are applied and a main clock gate section having a gate on which a pair of clock pulses inverted in phase from each other for shifting the data signals stored in said main shift gate section to a succeeding shift gate section are impressed, an inverter having the input connected to said main shift gate section output, and an auxiliary shift gate which includes an auxiliary shift gate section having the input and output connected to the output and input of said inverter and an auxiliary clock gate section having a gate on which clock pulses with inverted phases to those of the paired clock pulses for said main clock gate section are impressed; and the other shift register unit half comprising at least a main shift gate which includes a main shift gate section having an input to which output binary coded signals from said one shift register unit half are applied and a main clock gate section having a gate on which a pair of clock pulses inverted in phase from each other for shifting the data signals stored in said associated main shift gate section to a succeeding shift gate section are impressed, the improvement being that said both main shift gate sections, said both main clock gate sections, said inverter, said auxiliary shift gate section and said auxiliary clock gate section each comprise a complementary pair of insulated gate enhancement type field effect transistors.
Claim 3
Dependent Claim
170 words
A shift register according to claim 1 wherein said main shift gate section comprises a first complementary pair of P channel and N channel IGFET''s having the gates connected together to a corresponding input to be supplied with the binary coded signals and having the drains connected together to the input of said associated inverter or a succeeding main shift gate section; and said main clock gate section comprises a second complementary pair of IGFET''s constituted by a second P channel IGFET having the drain-source path connected between the source of said first P channel IGFET and a positive power source and having the gate impressed with a clock pulse of a predetermined phase, and a second N channel IGFET having the drain-source path connected between the source of said first N channel IGFET and a negative power source and having the gate impressed with a clock pulse of an inverted phase to that of said clock pulse to be impressed on the gate of said second P channel IGFET.
Claim 4
Dependent Claim
61 words
A shift register according to claim 1 wherein said inverter comprises a third complementary pair of P channel and N channel IGFET''s having the gates as well as the drains connected together, the source of said P channel IGFET being connected to a positive power source and the soUrce of said N channel IGFET being connected to a negative power source.
Claim 5
Dependent Claim
140 words
A shift register according to claim 3 wherein said inverter comprises not only the inverter section which includes said third complementary pair of P and N channel IGFET''s, but also a clock gate section which includes a fourth complementary pair of IGFET''s constituted by a fourth P channel IGFET having the drain-source path connected between the source of said third P channel IGFET and said positive power source; and a fourth N channel IGFET having the drain-source path connected between the source of said third N channel IGFET and said negative power source, the gates of said fourth P and N channel IGFET''s being impressed with clock pulses having respective inverted phases to those of said clock pulses to be impressed on the gates of said second P and N channel IGFET''s included in said associated main clock gate section.
Claim 6
Dependent Claim
153 words
A shift register according to claim 1 wherein said auxiliary shift gate section comprises a fifth complementary pair of P channel and N channel IGFET''s having the gates connected together to the output of said associated inverter and having the drains connected together to the input of said associated inverter; and said auxiliary clock gate section comprises a sixth complementary pair of IGFET''s constituted by a sixth P channel IGFET having the drain-source path connected between the source of said fifth P channel IGFET and a positive power source; and a sixth N channel IGFET having the drain-source path connected between the source of said fifth N channel IGFET and a negative power source, the gates of said sixth P and N channel IGFET''s being impressed with clock pulses having phases inverted with respect to those of said clock pulses to be impressed on the gates of said associated main clock gate section.
Claim 7
Dependent Claim
93 words
A shift register according to claim 1 wherein the other shift register unit half further includes an inverter and an auxiliary shift gate; and said main shift gate included in the other shift register unit half has the input connected to the output of said main shift gate included in said one shift register unit half, the output of said first-mentioned main shift gate being connected to the input of said associated inverter and said auxiliary shift gate having the input and output connected to the output and input of said associated inverter.
Claim 8
Dependent Claim
116 words
A shift register according to claim 2 wherein said main shift gate further includes at least one additional P channel IGFET having the drain-source path connected in parallel to the drain source path of said first P channel IGFET and at least one additional N channel IGFET having the drain-source path connected between the source of said first N channel IGFET and the drain of said second N channel IGFET, the gates of said additional P and N channel IGFET''s being connected together to an additional input to be supplied with additional binary coded signals separate from said first-mentioned binary coded signals, thereby effecting NAND/NOR function with respect to a plurality of binary coded input signals.
Claim 9
Dependent Claim
115 words
A shift register according to claim 2 wherein said main shift gate further includes at least one additional N channel IGFET having the drain-source path connected in parallel to the drain-source path of said first N channel IGFET and at least one additional P channel IGFET having the drain-source path connected between the source of said first P channel IGFET and the drain of said second P channel IGFET, the gates of said additional N and P channel IGFET''s being connected together to an additional input to be supplied with additional binary coded signals separate from said first-mentioned binary coded signals, thereby effecting NOR/NAND function with respect to a plurality of binary coded input signals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-09 | 1977-01-08 | 1977-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-09 | 1981-01-08 | 1981-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-09 | 1985-01-08 | 1985-07-10 | $7700.00 | Window Closed / Lapsed |