Patent US3745310A successfully refreshed from Google Patents.
US3745310A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Magnetic tape read-out system
Assignee: CIE INTERNATIONALE POUR L INFORMATIQUE FR
•
Filing: 1971-03-16
•
Granted: 1973-07-10
•
Expires: 1991-03-16
Abstract
Abstract Chronometric controls are provided for detecting the occurrence of predetermined conditions of appearances of significant pulses in any character read out from the magnetic tape and for so modifying therefrom the length of the assembly operation of each read out character that the effect of the dynamic skew is substantially compensated in such assemblies.
Inventors
- 👤 P Laborde
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:45
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
367 words
In a system processing characters read out from a magnetic tape which is continuously driven at a substantially constant speed and on which such characters are spaced apart by a substantially constant distance defining a substantially constant period T of the occurrence of the read out characters, each character comprising as many bits as there are longitudinal tracks on the tape and the bit-significant pulses therefrom being stored in an assembly register provided with output gates which are unblocked by a signal marking the end of an assembly period, shorter than T, starting from the time instant of each first appearing bit-significant pulse of a pre-determined character, the combination of: a chronometric organization activated at the beginning of each such time instant for a period the maximum duration of which exceeds the said period T and reset at each such time instant just prior to activation thereof; first and second outputs in said organization, the first activated at a time instant (T- theta A) less than T though higher than a predetermined value TA, the second activated at a time instant (T+ theta R) greater than T though lower than (TTA); first and second members respectively memorizing the activations of said first aNd second outputs within a period of activity of said organization; first and second means reading the conditions of the said first and second members on such a time instant of each first appearing bit-significant pulse of a character prior to resetting of the said organization; a logical operator arrangement having first and second control inputs respectively connected to the outputs of the said first and second reading means and having an output connected to unblocking inputs of the assembly register output gates and issuing, within the period of activity of said organization initiated by said first appearing bit significant pulse occurrence, an assembly period end marking signal at a time instant which is: TA in activated condition of its first control input and unactivated condition of its second control input; (TA + Alpha theta A) in unactivated condition of its first input; (TA - Beta theta R) in activated condition of its second input. Alpha and Beta being numerical coefficients no greater than 1.
Claim 2
Dependent Claim
367 words
In a system processing characters read out from a magnetic tape which is continuously driven at a substantially constant speed and on which such characters are spaced apart by a substantially constant distance defining a substantially constant period T of the occurrence of the read out characters, each character comprising as many bits as there are longitudinal tracks on the tape and the bit-significant pulses therefrom being stored in an assembly register provided with output gates which are unblocked by a signal marking the end of an assembly period, shorter than T, starting from the time instant of each first appearing bit-significant pulse of a pre-determined character, the combination of: a chronometric organization activated at the beginning of each such time instant for a period the maximum duration of which exceeds the said period T and reset at each such time instant just prior to activation thereof; first and second outputs in said organization, the first activated at a time instant (T- theta A) less than T though higher than a predetermined value TA, the second activated at a time instant (T+ theta R) greater than T though lower than (TTA); first and second members respectively memorizing the activations of said first aNd second outputs within a period of activity of said organization; first and second means reading the conditions of the said first and second members on such a time instant of each first appearing bit-significant pulse of a character prior to resetting of the said organization; a logical operator arrangement having first and second control inputs respectively connected to the outputs of the said first and second reading means and having an output connected to unblocking inputs of the assembly register output gates and issuing, within the period of activity of said organization initiated by said first appearing bit significant pulse occurrence, an assembly period end marking signal at a time instant which is: TA in activated condition of its first control input and unactivated condition of its second control input; (TA + Alpha theta A) in unactivated condition of its first input; (TA - Beta theta R) in activated condition of its second input. Alpha and Beta being numerical coefficients no greater than 1.
Claim 3
Dependent Claim
116 words
Combination according to claim 1, wherein said chronometric organization includes a third output activated at a time instant theta D lower than (TA- Beta theta R), a third member memorizing the activation of said third output within a period of activity of said organization, third reading means reading the condition of said third member at each occurrence of a bit-significant pulse and blocked after the first activated condition read-out of said third member, and in which said logical operator arrangement comprises a third control input connected to the output of said third reading means which, when activated, delays by a time interval gamma theta D the time instant of issuance of said assembly period end signal.
Claim 4
Dependent Claim
16 words
Combination according to claim 1, wherein said predetermined time interval TA is substantially equal to T/2.
Claim 5
Dependent Claim
21 words
Combination according to claim 2, wherein the said Alpha , Beta and gamma coefficients are each equal to substantially 1/2 .
Claim 6
Dependent Claim
163 words
Combination according to claim 2, wherein in addition to said first, second and third control outputs, said chronometric organization is provided with additional pulse outputs respectively activated at the time instants (TA - Beta theta R), (TA - Beta theta R + gamma theta D), TA, (TA + gamma theta D), (TA + Alpha theta A), (TA + Alpha theta A + gamma theta D), and wherein the said logical operator arrangement comprises as many gates the inputs of which are respectively connected to said additional pulse outputs and the outputs of which are OR-connected to the output of issuance of the said assembly period end marking signal, each of the said first, second and third reading means memorizing their respective reading results for application to their outputs within the period of activity of said organization initiated by the occurrence of the said first appearing bit-significant pulse of a character, and said outputs being selectively connected in unblocking control combinations to said gates.
Claim 7
Dependent Claim
67 words
Combination according to claim 5, wherein memorization of the results of said first and second reading means is made on members relaying the conditions of the corresponding said first and second output activation memorizing members when reset by the reading operation proper whereas the memorization of the result of the said third reading means is directly obtained on the outputs of said third activation memorizing member proper.
Claim 8
Dependent Claim
142 words
Combination according to claim 2, wherein said logical operator arrangement comprises a settable count pulse counter having its pulse count output connected to the said issuance output of the assembly period end marking signal, means feeding said pulse counter during each period of activity of the chronometric organization and means for resetting said counter to a TA count prior to activation of the said first and second reading means, a firSt setting modifying input increasing TA by Alpha theta A when activated from the reading of the condition of the said first member, a second setting modifying input decreasing TA by Beta theta R when activated from the reading of the condition of the said second member and a third setting modifying input increasing TA by gamma theta D when activated from the reading of the condition of the said third member.
Claim 9
Dependent Claim
26 words
Combination according to claim 7, wherein the said settable count pulse counter consists of a decounter activating its output at its passage by a zero count.
Claim 10
Dependent Claim
43 words
Combination according to claim 7, wherein each of the said setting modifying inputs comprises a permanent count store read on the activation of the output of the corresponding member condition reading means and having output count setting modifying connections to said pulse counter.
Claim 11
Dependent Claim
169 words
Combination according to claim 1, wherein said chronometric organization comprises a clock pulse counter, a logical OR circuit receiving all the bit-significant pulses, a first output from said OR circuit to a first gate and a second and delayed output of said OR circuit to an activation input of a two-condition member the reset input of which is connected to the output of said first gate, a second gate receiving an uninterrupted series of clock pulses and controlled to unblocking from an activated condition marking output of the said two-condition member and having an output connected to the pulse count input of said counter, means blocking said first gate on the activation of the output of the said second gate and means, connected to the output of the said logical operator arrangement, unblocking said first gate upon activation thereof, the output of said first gate being connected to the inputs of the said first and second member condition reading means and to the reset of said clock pulse counter.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-09 | 1977-01-08 | 1977-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-09 | 1981-01-08 | 1981-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-09 | 1985-01-08 | 1985-07-10 | $7700.00 | Window Closed / Lapsed |