US3744050A
Expired / Lapsed
US
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Apparatus for providing an analog output in response to a digital input
Assignee: Lear Siegler Inc
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Filing: 1970-11-23
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Granted: 1973-07-03
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Expires: 1990-11-23
Abstract
Abstract An analog output signal is provided in response to a digital input signal by means which include a read only memory which has been programmed to provide an analog function of an input signal and a binary scaling means, such as an R-2R ladder network connected to the output of the memory. The memory may be programmed to provide a sinusoidal function of the digital input signal whereby a digital-to-resolver conversion occurs and the analog resolver equivalent of the digital input is provided. Alternatively, a filter response, such as a band pass response, may be provided for an analog signal by programming the memory to provide an attenuation function in response to a digital input signal which is associated with the value of the input frequency of the analog signal, the analog signal being fed through the output stage of the memory. Clearly, the memory may be programmed for other applications in which an analog output signal is provided in response to a digital input signal.
Inventors
- 👤 G Hedrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:39
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/665; G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/035; G06F1/0353
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
303 words
An apparatus for providing an analog output signal in response to a digital input signal comprising: a read only memory means having an input portion and an output portion, said digital signal being a binary signal whose content comprises a plurality of bits, said plurality of bits being fed to said input portion, said input portion comprising a preprogrammed matrix array programmed to provide an analog function in response to said digital input signal, said output portion comprising a plurality of bistable switching means, one bistable switching means being provided for each of said bits, each of said bistable switching means including a serially coupled sink-source pair of field effect transistors, each having a source electrode, a drain electrode and a gate electrode with the source electrode of one transistor of said transistor pair being coupled at a junction to the drain electrode of the other transistor of said transistor pair; binary scaling means operatively connected to said memory means output portion, said scaling means comprising a ladder network having a plurality of branches, each of said branches being operatively connected to an associated one of said junction points for scaling said digital binary input to provide said analog output in accordance with said analog function, each of said bistable switching means having an output state in which an output signal is provided to said associated ladder network branch and another state in which an output signal is not provided to said associated branch, said analog output being dependent on the state of each of said bistable switching means, said state being dependent on said function and said binary signal content; and summing means operatively associated with said scaling means branches for providing said analog output from a sum of the outputs of said branches to which an output signal has been provided.
Claim 2
Independent Claim
303 words
An apparatus for providing an analog output signal in response to a digital input signal comprising: a read only memory means having an input portion and an output portion, said digital signal being a binary signal whose content comprises a plurality of bits, said plurality of bits being fed to said input portion, said input portion comprising a preprogrammed matrix array programmed to provide an analog function in response to said digital input signal, said output portion comprising a plurality of bistable switching means, one bistable switching means being provided for each of said bits, each of said bistable switching means including a serially coupled sink-source pair of field effect transistors, each having a source electrode, a drain electrode and a gate electrode with the source electrode of one transistor of said transistor pair being coupled at a junction to the drain electrode of the other transistor of said transistor pair; binary scaling means operatively connected to said memory means output portion, said scaling means comprising a ladder network having a plurality of branches, each of said branches being operatively connected to an associated one of said junction points for scaling said digital binary input to provide said analog output in accordance with said analog function, each of said bistable switching means having an output state in which an output signal is provided to said associated ladder network branch and another state in which an output signal is not provided to said associated branch, said analog output being dependent on the state of each of said bistable switching means, said state being dependent on said function and said binary signal content; and summing means operatively associated with said scaling means branches for providing said analog output from a sum of the outputs of said branches to which an output signal has been provided.
Claim 3
Dependent Claim
89 words
An apparatus in accordance with claim 1 wherein said apparatus further includes a source of analog input signal, said analog input signal having an associated frequency, said analog input source being operatively connected to said output portion for applying said analog input signal thereto, said analog function is an attenuation function, said digital input signal is a function of said associated frequency, and said output portion provides said analog output signal in accordance with said analog input signal and said attenuation function, whereby said analog input signal is filtered.
Claim 4
Dependent Claim
45 words
An apparatus in accordance with claim 2 wherein said apparatus includes a means operatively connected to said analog input source and said memory means input portion for providing said digital input signal to said memory means input portion as a function of said associated frequency.
Claim 5
Dependent Claim
33 words
An apparatus in accordance with claim 3 wherein said digital input providing means includes means for determining said associated frequency and providing a digital equivalent of said associated frequency as said digital input.
Claim 6
Dependent Claim
18 words
An apparatus in accordance with claim 2 wherein said analog input is applied to said uncoupled drain electrode.
Claim 7
Dependent Claim
35 words
An apparatus in accordance with claim 5 wherein said summing means has an input and an output, said summing means input being operatively connected to said scaling means for providing said filtered analog output therefrom.
Claim 8
Dependent Claim
18 words
An apparatus in accordance with claim 2 wherein said binary scaling means is an R-2R impedance ladder network.
Claim 9
Dependent Claim
18 words
An apparatus in accordance with claim 1 wherein said binary scaling means is an R-2R impedance ladder network.
Claim 10
Dependent Claim
47 words
An apparatus in accordance with claim 1 wherein said memory means has an operating state and a protection state, no output being provided from said output portion in said protection state, said memory means output portion being capable of providing said analog output in said operating state.
Claim 11
Dependent Claim
29 words
An apparatus in accordance with claim 9 further comprising means for maintaining said memory means in said operating state, said maintaining means being operatively connected to said memory means.
Claim 12
Dependent Claim
97 words
An apparatus in accordance with claim 10 wherein a source of an analog input signal having a most positive deviation is operatively connected to said output portion for feeding said analog input signal thereto, said memory means is an MOS memory means having a substrate and an associated substrate potential, and said maintaining means includes means for referencing said analog input signal at a potential of a value such that said most positive deviation of said analog input signal is never greater than said associated substrate potential, whereby said MOS means is maintained in said operating state.
Claim 13
Dependent Claim
61 words
An apparatus in accordance with claim 11 wherein said analog input signal has an associated frequency, said analog function is an attenuation function, said digital input signal is a function of said associated frequency, and said output portion provides said analog output signal in accordance with said analog input signal and said attenuation function, whereby said analog input signal is filtered.
Claim 14
Dependent Claim
75 words
An apparatus in accordance with claim 10 wherein said memory means includes a protection means having a conduction state and a non-conduction state, said protection means being operatively connected to said output portion, said memory means being in said operating state when said protection means is in said non-conduction state and in said protection state when said protection means is in said conduction state, said maintaining means maintaining said protection means in said non-conduction state.
Claim 15
Dependent Claim
28 words
An apparatus in accordance with claim 1 wherein said scaling means comprises an impedance means, said analog output signal has a magnitude proportional to said scaling means impedance.
Claim 16
Dependent Claim
85 words
An apparatus in accordance with claim 11 wherein said summing means has an input and an output, said summing means input being operatively connected to said scaling means, said scaling means having a total impedance value and a scaled impedance value equivalent to a binary equivalent of said digital input, said summing means output being said analog output, said summing means output having a magnitude proportional to said reference potential and a ratio of said scaling means scaled impedaNce to said scaling means total impedance.
Claim 17
Dependent Claim
151 words
An apparatus in accordance with claim 11 wherein said summing means has an input and an output, said summing means input being operatively connected to said memory means output portion, said scaling means having a total impedance value and a scaled impedance value equivalent to a binary equivalent of said digital input, said summing means output being said analog output, said summing output having a magnitude proportional to said reference potential and a ratio of said scaling means scaled impedance to said scaling means total impedance, said summing means being a high gain operational amplifier means, said memory means is an MOS memory means having a substrate and an associated substrate potential, said summing means input being operatively connected to said scaling means, and said reference potential maintaining said uncoupled source and drain electrodes at a potential close to substrate potential, whereby said MOS means is maintained in said operating state.
Claim 18
Dependent Claim
38 words
An apparatus in accordance with claim 1 wherein said input portion is programmed to provide a sinusoidal function of said digital input signal, said analog output signal being a synchro output signal proportional to said digital input signal.
Claim 19
Dependent Claim
85 words
An apparatus in accordance with claim 17 wherein said plurality of bits includes digital angular information bits and quadrant location bits, said angular information bits indicating a digital angular equivalent between 0* and 90* and said quadrant location bits indicating a quadrant of 360* in which said equivalent digital angle is located, said apparatus further including means for providing said synchro output signal as an analog sinusoidal function of a digital angle between 0* and 360* from said angular information and said quadrant location bits.
Claim 20
Dependent Claim
85 words
An apparatus in accordance with claim 18 wherein said read only memory means input portion is programmed to provide said analog sinusoidal function as a function of a digital angle between 0* and 90*, and said analog 0* to 360* analog sinusoidal function providing means includes multiplexer switching means operatively connected to said binary scaling means and said digital input for providing said 0* to 360* analog function from said sinusoidal function of a digital angle between 0* and 90* and said quadrant location bits.
Claim 21
Dependent Claim
75 words
An apparatus in accordance with claim 19 wherein said 0* to 360* analog sinusoidal function providing means includes a transformer means having a center-tapped secondary winding and a primary winding, said primary winding being operatively connected to an input of said multiplexer and to said binary scaling means for providing said 0* and 90* sinusoidal function as an input to said multiplexer, and said quadrant locations bits being provided as another input to said multiplexer.
Claim 22
Dependent Claim
15 words
An apparatus in accordance with claim 2 wherein said attenuation function is a non-linear function.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-02 | 1977-01-01 | 1977-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-02 | 1981-01-01 | 1981-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-02 | 1985-01-01 | 1985-07-03 | $7700.00 | Window Closed / Lapsed |