Pulse doppler moving-target radar

Claim 3

The method of claim 1 wherein the digital signals are stored in a memory of the type in which the storing of a later-stored signal affects the storing of an earlier-stored signal, the said method comprising temporarily removing from said memory and holding in a temporary holding register all earlier-stored signals before a later-stored signal is stored, and simultaneously with the later storing of said later-stored signal restoring to the memory the earlier-stored signals held in said temporary holding register.

Claim 4

The method of claim 1 wherein in the conversion from digital to analogue signals the predetermined number of the plural bit words stored during a plurality of successive intervals are converted to analogue signals simultaneously.

Claim 5

The method of claim 1 wherein the digital signals are removed as a predetermined number of plural bit words in substantially the same order in which the signals are stored individually in the locations.

Claim 6

The method of claim 1 wherein the memory core is a three-dimensional array of storing elements, extending in length, width and heighth, and wherein the converted digital signals are stored in succession in the elements in successive rows along the heighth dimension, which rows extend in length and width and wherein on removal of the digital signals, the digital signals are removed from the rows in the order in which they are stored but a plurality of digital signals extending in width are removed simultaneously on each removal operation.

Claim 7

A puLse-doppler moving-target radar system including a receiver for receiving signals from targets, a plurality of range channels connected to said receiver, separate range gates connected in each of said range channels enabling said channels in succession, during sampling intervals, each channel to pass in its turn a sample of a signal, if any received, corresponding to the range of said last-named channel, sampling means in said channels, each to pass said samples received by said receiver during the corresponding sampling intervals, cycles of said samples being passed repeatedly through said channels each in its turn during each of a plurality of successive intervals, a separate analogue-to-digital converter connected to each channel for converting the samples of the signals passed by said last-named channel, in the succession in which they are passed, into digital magnitudes, memory means connected to said analogue-to-digital converter, first means connected to said memory means for actuating said memory means to store the digital magnitudes of said converter in the order in which they are passed by said channels, each magnitude being stored in a predetermined address in said memory means which address corresponds to the order in which said last-named magnitude is stored, and each address and each magnitude being stored in said address as a plural bit word, digital-to-analogue converting means connected to said memory means, second means connected to said memory means for actuating said memory means to pass to said digital-to-analogue converting means the digital magnitudes for each range channel in its turn in succession, a predetermined number of said plural bit words being passed in succession for each said range channel, and unitary filter means connected to said digital-to-analogue converting means for receiving, in filtering relationship, the analogue signals from said digital-to-analogue converting means channel by channel in the order in which said digital-to-analogue converter means receives the digital signals.

Claim 8

A puLse-doppler moving-target radar system including a receiver for receiving signals from targets, a plurality of range channels connected to said receiver, separate range gates connected in each of said range channels enabling said channels in succession, during sampling intervals, each channel to pass in its turn a sample of a signal, if any received, corresponding to the range of said last-named channel, sampling means in said channels, each to pass said samples received by said receiver during the corresponding sampling intervals, cycles of said samples being passed repeatedly through said channels each in its turn during each of a plurality of successive intervals, a separate analogue-to-digital converter connected to each channel for converting the samples of the signals passed by said last-named channel, in the succession in which they are passed, into digital magnitudes, memory means connected to said analogue-to-digital converter, first means connected to said memory means for actuating said memory means to store the digital magnitudes of said converter in the order in which they are passed by said channels, each magnitude being stored in a predetermined address in said memory means which address corresponds to the order in which said last-named magnitude is stored, and each address and each magnitude being stored in said address as a plural bit word, digital-to-analogue converting means connected to said memory means, second means connected to said memory means for actuating said memory means to pass to said digital-to-analogue converting means the digital magnitudes for each range channel in its turn in succession, a predetermined number of said plural bit words being passed in succession for each said range channel, and unitary filter means connected to said digital-to-analogue converting means for receiving, in filtering relationship, the analogue signals from said digital-to-analogue converting means channel by channel in the order in which said digital-to-analogue converter means receives the digital signals.

Claim 9

The apparatus of claim 6 wherein the memory means is of the type in which the storing of a later-stored signal affects an earlier-stored signal, the said apparatus including a temporary holding register and means cooperative with said memory means and temporary holding register for transferring all earlier-stored signals subject to be affected by a later-stored signal to said temporary holding register and thereafter, responsive to the storing in said memory means of said later-stored signal, simultaneously with said later-stored signal restoring to said memory means said transferred earlier-stored signals.

Claim 10

The apparatus of claim 6 wherein the memory means includes a plurality of memory elements which may be regarded as located in blocks in a parallelapiped, each block having a location in a column rows of the parallela-piped and wherein the first means includes a first counter for setting the row of columns along one dimension of a block of a plurality of blocks of columns where a memory element to receive a signal is located, a second counter for setting the position along the row of columns where the said last-named element is located, a third counter for setting the block of columns in which the last-named element is located, and a fourth counter for setting the position along the selected column in which the last-named element is located.

Claim 11

The apparatus of claim 8 wherein the second means includes the third, fourth, and first counters and the third counter actuates the memory means to transfer all signals in a row, of a column selected by the fourth and first counters simultaneously to the digital-to-analogue converter.

Claim 12

The system of claim 6 wherein the memory means is a three dimensional array of memory elements arrayed in length, width and heighth, and wherein the first means stores the digital magnitudes successively in elements of successive rows extending along the heighth dimension, said rows extending in length and width, and wheRein the second means actuate the memory means to pass the digital magnitude stored in rows in the order in which the magnitudes are stored in the rows, but for each row, all magnitudes along the width of said last-named row simultaneously.