Burst and single error detection and correction system

Claim 2

In a data communication system, the combination including a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said record means recording only one burst error for correcting the burst error in said data segment at the address indicated in said burst error address register with the parity word generated by said parity word generator, and means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error.

Claim 3

The combination claimed in claim 1 including means responsive to the detection of a single bit error by said checking means for correcting said single bit error.

Claim 4

In a data communication system, the combination including a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said recording means recording only one burst error for shifting said data segment out of said shift register one bit at a time, said shift counter responsive to shift of data bits out of said shift register for counting said bits of data, means for comparing the count of bits shifted out of said shift counter with the contents of said burst error address register and indicating a match between them, means responsive to the indication of a match by said comparison means for exclusive oring said data bits and said corresponding parity word to complement said burst errors, and means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error.

Claim 5

In a data communication system, the combination including a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said recording means recording only one burst error for shifting said data segment out of said shift register one bit at a time, said shift counter responsive to shift of data bits out of said shift register for counting said bits of data, means for comparing the count of bits shifted out of said shift counter with the contents of said burst error address register and indicating a match between them, means responsive to the indication of a match by said comparison means for exclusive oring said data bits and said corresponding parity word to complement said burst errors, and means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error.

Claim 6

The combination claimed in claim 3 including means responsive to the detection of a single bit error by said checking means for correcting said single bit error.

Claim 7

In a data communication system including, a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data sigNal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said record means recording only one burst error for correcting the burst error in said data segment at the address indicated in said burst error address register with the parity word generated by said parity word generator, means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error, each data segment having an associated parity word and a check word, a parity word register, a check word register, means for shifting the parity word associated with said data segment into said parity word register and the check word associated with said data segment into said check word register, a parity error bit counter, a check word generator, means responsive to the correction of a burst error in said data segment by said correction means for feeding said corrected data segment through said parity word generator and said check word generator for detecting a single bit error, said parity error bit counter responsive to the detection of a single bit error for indicating the number of single bit errors in said data segment, and means responsive to the detection of a single bit error for correcting said single bit error in said data segment with said check word generator.

Claim 8

In a data communication system including, a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data sigNal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said record means recording only one burst error for correcting the burst error in said data segment at the address indicated in said burst error address register with the parity word generated by said parity word generator, means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error, each data segment having an associated parity word and a check word, a parity word register, a check word register, means for shifting the parity word associated with said data segment into said parity word register and the check word associated with said data segment into said check word register, a parity error bit counter, a check word generator, means responsive to the correction of a burst error in said data segment by said correction means for feeding said corrected data segment through said parity word generator and said check word generator for detecting a single bit error, said parity error bit counter responsive to the detection of a single bit error for indicating the number of single bit errors in said data segment, and means responsive to the detection of a single bit error for correcting said single bit error in said data segment with said check word generator.