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US3742260A
Expired / Lapsed
US
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M. o. s. transistor circuits for pulse-shaping
Assignee: EUROP SEMICONDUCTERUS MICROELE
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Filing: 1971-05-06
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Granted: 1973-06-26
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Expires: 1991-05-06
Abstract
Abstract A voltage doubler comprises an input terminal to which is applied a square wave voltage, taking a positive voltage value during recurrent time intervals of fixed duration and the zero value, during recurrent time intervals of fixed duration. Two resistance capacitance circuits are connected to this terminal. The first circuit comprises a first resistor and first capacitor series connected between the ground and the input terminal. The second circuit comprises a resistor, a diode series connected between the input terminal and the output terminal, and a capacitor connected in series with the capacitor of the first circuit between the output terminal and the ground. The time constants of the first and second circuits are appropriately chosen.
Inventors
- 👤 J Boudry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:31
CPC Classifications
G; G04; G04G; G04G99/00; G04G99/003; G04C; G04C3/00; G04C3/14; G04G19/00; G04G19/02; G04G19/04; H; H03; H03K; H03K5/00; H03K5/01
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
143 words
A voltage doubler comprising in combination: one input and one output terminal, a first circuit comprising a first resistance means and a first capacitor, series connected for connecting said input terminal to the ground, said first circuit having a first time constant, and said first capacitor having a grounded electrode, and another electrode, a second circuit comprising a second resistance means and rectifying means series connected for conducting a current flowing from said input terminal to said output terminal and a second capacitor directly connecting said output terminal to said another electrode, said second circuit having a second time constant substantially higher than said first time constant, and means for applying at said input terminal, a square wave voltage having a predetermined recurrence frequency and taking a positive level, during first time intervals having a duration substantially greater than said second time constant.
Claim 2
Dependent Claim
143 words
A voltage doubler comprising in combination: one input and one output terminal, a first circuit comprising a first resistance means and a first capacitor, series connected for connecting said input terminal to the ground, said first circuit having a first time constant, and said first capacitor having a grounded electrode, and another electrode, a second circuit comprising a second resistance means and rectifying means series connected for conducting a current flowing from said input terminal to said output terminal and a second capacitor directly connecting said output terminal to said another electrode, said second circuit having a second time constant substantially higher than said first time constant, and means for applying at said input terminal, a square wave voltage having a predetermined recurrence frequency and taking a positive level, during first time intervals having a duration substantially greater than said second time constant.
Claim 3
Dependent Claim
93 words
A voltage doubler as claimed in claim 1, wherein said first resistance meaNs comprise a first MOS transistor, having its source connected to said input terminal, its drain connected to said first capacitor, and a gate, said second resistance means and said rectifying means comprising a second MOS transistor having a gate connected to a D.C. supply, supplying a constant voltage, a source connected to said input terminal and a drain to said output terminal, a third MOS transistor having its source grounded, its drain connected to the drain of said second transistor.
Claim 4
Dependent Claim
60 words
A voltage doubler as claimed in claim 2, wherein said voltage applying means comprise a fourth MOS transistor having a gate for receiving a recurrent train of positive polarity pulses, having said recurrent frequency, a source grounded, and a drain connected to said input terminal, and means for receiving said pulses, and for generating in response, said square wave voltage.
Claim 5
Dependent Claim
80 words
A voltage doubler as claimed in claim 3, wherein said pulse receiving means comprise a fifth transistor, having its gate and source connected to said D.C. voltage source, its drain to the gate of said first transistor, and a third capacitor for connecting said last mentioned drain to said input terminal, and a sixth transistor, having a source connected to said D.C. voltage source, a drain to said input terminal, and a drain connected to drain of said fifth transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-25 | 1976-12-25 | 1977-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-25 | 1980-12-25 | 1981-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-25 | 1984-12-25 | 1985-06-26 | $7700.00 | Window Closed / Lapsed |