Abstract A binary code communication system in which the binary bits are formatted for transmission into a sequence of code elements, each code element comprising four bits beginning with a timing bit having a first binary value followed by two consecutive data bits in turn followed by a second timing bit having a second binary value. One or more encoders receive binary data bits from a plurality of parallel inputs, serially convert the binary data bits into a data string, generate appropriate timing bits, and logically gate the data bits and timing bits into code elements. The code elements are grouped into words for transmission. One or more decoders receive, analyze and decode the transmitted encoded data sampling the bit values and bit transitions within each code element to determine the occurrence of errors. Error-free decoded data is passed to output while erroneous data is flagged. A system for transmission of encoded data from a plurality of remote stations on a single channel is described.
An automated method for encoding binary data comprising: generating a first train of two level waveform timing pulses of alternating bInary value, each alternating value having a duration equal to the desired code bit duration; generating a second train of two level waveform timing pulses of alternating binary value, said second train having a period equal to one desired element comprising four code bits; scanning binary data bits at a plurality of parallel data inputs and serially converting the data into a string of data bits; and logically gating the first and second trains of timing pulses and the data bit string to form a sequence of code elements, each code element comprising four bits beginning with a timing bit having a first binary value followed by two consecutive data bits in turn followed by a second timing bit having a second binary value.
Claim 2
Dependent Claim
144 words
An automated method for encoding binary data comprising: generating a first train of two level waveform timing pulses of alternating bInary value, each alternating value having a duration equal to the desired code bit duration; generating a second train of two level waveform timing pulses of alternating binary value, said second train having a period equal to one desired element comprising four code bits; scanning binary data bits at a plurality of parallel data inputs and serially converting the data into a string of data bits; and logically gating the first and second trains of timing pulses and the data bit string to form a sequence of code elements, each code element comprising four bits beginning with a timing bit having a first binary value followed by two consecutive data bits in turn followed by a second timing bit having a second binary value.
Claim 3
Dependent Claim
153 words
An encoder for encoding binary data comprising: means for generating a first train of two level waveform timing pulses of alternating binary value, each alternating valve having a duration equal to the desired code bit duration; means for generating a second train of two level waveform timing pulses of alternating binary value, said second train having a period equal to one desired code element comprising four code bits; means for scanning binary data bits at a plurality of parallel data inputs and serially converting the data into a string of data bits; and logic circuit means for gating the first and second trains of timing pulses and the data bit string to form a sequence of code elements, each code element comprising four bits beginning with a timing bit having a first binary value followed by two consecutive data bits in turn followed by a second timing bit having a second binary value.
Claim 4
Dependent Claim
153 words
An encoder for encoding binary data comprising: means for generating a first train of two level waveform timing pulses of alternating binary value, each alternating valve having a duration equal to the desired code bit duration; means for generating a second train of two level waveform timing pulses of alternating binary value, said second train having a period equal to one desired code element comprising four code bits; means for scanning binary data bits at a plurality of parallel data inputs and serially converting the data into a string of data bits; and logic circuit means for gating the first and second trains of timing pulses and the data bit string to form a sequence of code elements, each code element comprising four bits beginning with a timing bit having a first binary value followed by two consecutive data bits in turn followed by a second timing bit having a second binary value.