Patent US3739375A successfully refreshed from Google Patents.
US3739375A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Auxiliary circuit for analog to digital coder
Assignee: Alcatel Lucent NV
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Filing: 1969-04-10
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Granted: 1973-06-12
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Expires: 1989-04-10
Abstract
Abstract A high-gain differential amplifier is used as a comparator in a PCM coder. The amplifier may oscillate during the time reserved for the charge of the holding capacitor. According to the invention an auxiliary circuit delivers, during that time, a voltage which is higher than the maximum possible value of the signal to be coded. This high voltage is applied to the comparator in order to block it.
Inventors
- 👤 A Chatelon
- 👤 M Regnier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:24
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/044; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
211 words
An auxiliary circuit for analog to digital coders comprising: first means for sampling analog signals at predetermined periodic intervals and for storing samples derived from said signals on a capacitor; second means responsive to a sample having been stored for generating a PCM word having n digits, where n is an integer greater than one; third means coupled to said second means to decode said generated PCM word, said third means including n current generators, each of said generators being controlled by a different one of said n digits of said generated PCM word, and a ladder attenuator appropriately coupled to said n current generators to produce an output voltage proportional to said generated PCM word; said second means including comparator means having one input thereof coupled to said capacitor and the other input thereof coupled to said ladder attenuator to generate said PCM word by comparing the amplitude of said stored samples with said output voltage; and a current generator coupled to said ladder attenuator to produce, in the intervals between sampling, a blocking voltage having a magnitude higher than the maximum possible magnitude of said signals to be coded, said blocking voltage being coupled to said other input of said comparator means to prevent oscillations of said comparator means.
Claim 2
Dependent Claim
211 words
An auxiliary circuit for analog to digital coders comprising: first means for sampling analog signals at predetermined periodic intervals and for storing samples derived from said signals on a capacitor; second means responsive to a sample having been stored for generating a PCM word having n digits, where n is an integer greater than one; third means coupled to said second means to decode said generated PCM word, said third means including n current generators, each of said generators being controlled by a different one of said n digits of said generated PCM word, and a ladder attenuator appropriately coupled to said n current generators to produce an output voltage proportional to said generated PCM word; said second means including comparator means having one input thereof coupled to said capacitor and the other input thereof coupled to said ladder attenuator to generate said PCM word by comparing the amplitude of said stored samples with said output voltage; and a current generator coupled to said ladder attenuator to produce, in the intervals between sampling, a blocking voltage having a magnitude higher than the maximum possible magnitude of said signals to be coded, said blocking voltage being coupled to said other input of said comparator means to prevent oscillations of said comparator means.
Claim 3
Dependent Claim
59 words
A circuit according to claim 1, further including a register having n stages to store a different one of said n digits of said generated PCM word; and logic circuit means coupled to the output of said comparator to couple said n digits of said generated PCM word to the appropriate one of said n stages of said register.
Claim 4
Dependent Claim
48 words
A circuit according to claim 2, wherein said comparator means includes a higher gain differential amplifier having one input thereof coupled to said capacitor to receive said stored samples and the other input thereof coupled to said ladder attenuator to receive said output voltage and said blocking voltage.
Claim 5
Dependent Claim
22 words
A circuit according to claim 3, wherein said register is cleared and said capacitor is discharged when said blocking voltage is produced.
Claim 6
Dependent Claim
48 words
A circuit according to claim 1, wherein said comparator means includes a high gain differential amplifier havIng one input thereof coupled to said capacitor to receive said stored samples and the other input thereof coupled to said ladder attenuator to receive said output voltage and said blocking voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-11 | 1976-12-11 | 1977-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-11 | 1980-12-11 | 1981-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-11 | 1984-12-11 | 1985-06-12 | $7700.00 | Window Closed / Lapsed |