Demodulating circuit employing phase shifting techniques

Claim 2

A circuit for decoding data represented by different frequencies in an input signal, said circuit comprising: means responsive to the frequency of said input signal for providing a signal having various phase differences with said input signal, each of said phase differences occurring in response to a different one of said input signal frequencies; means for detecting each of said phase differences; said frequencyresponsive means comprising an operational amplifier having an inverting input and a non-inverting input, and a filter connected in a feedback loop between said inverting input and said amplifier output, and wherein said input signal is applied to said non-inverting input.

Claim 3

The circuit as recited in claim 1 wherein said frequency-responsive means further comprises another filter connected to said non-inverting input and through which said input signal is applied to said operational amplifier.

Claim 4

A circuit for decoding data represented by different frequencies in an input signal, said circuit comprising: means responsive to the frequencies of said input signal for providing a signal having various phase differences with said input signal, each of said phase differences occurring in response to a different one of said input signal frequencies; means for detecting each of said phase differences; said input signals occurring at two different frequencies; said frequency responsive means providing a signal when said input signal is at one of said two frequencies and lags said input signal when said input signal is at the other of said two frequencies; said detecting means providing an output signal indicative of whether the signal from said frequency responsive means lags or leads said input signal, said detecting means comprising: a. first circuit means for receiving said input signal and the signal from said frequency-responsive means, said first circuit means being bistable for first periods of time while receiving said signals, the state of said first circuit during said first periods being dependent on which of said signals is leading; b. second circuit means for receiving said input signal and the signal from said frequency-responsive means, said second circuit means being bistable for second periods of time while receiving said signals, the state of said second circuit means during said second periods being dependent on which of said signals is leading; and c. means for providing an output signal indicative of the state of said first circuit means during said first periods and of the state of said second circuit means during said second periods.

Claim 5

A circuit for decoding data represented by different frequencies in an input signal, said circuit comprising: means responsive to the frequencies of said input signal for providing a signal having various phase differences with said input signal, each of said phase differences occurring in response to a different one of said input signal frequencies; means for detecting each of said phase differences; said input signals occurring at two different frequencies; said frequency responsive means providing a signal when said input signal is at one of said two frequencies and lags said input signal when said input signal is at the other of said two frequencies; said detecting means providing an output signal indicative of whether the signal from said frequency responsive means lags or leads said input signal, said detecting means comprising: a. first circuit means for receiving said input signal and the signal from said frequency-responsive means, said first circuit means being bistable for first periods of time while receiving said signals, the state of said first circuit during said first periods being dependent on which of said signals is leading; b. second circuit means for receiving said input signal and the signal from said frequency-responsive means, said second circuit means being bistable for second periods of time while receiving said signals, the state of said second circuit means during said second periods being dependent on which of said signals is leading; and c. means for providing an output signal indicative of the state of said first circuit means during said first periods and of the state of said second circuit means during said second periods.

Claim 6

The circuit as recited in claim 3 wherein said output signal providing means comprises: a. means for providing a first timing pulse during each of said first periods; b. means for providing a second timing pulse during each of said second periods; and c. bistable circuit means adapted to respond to the state of said first circuit means in response to each of said first timing pulses, said bistable circuit means also being adapted to respond to the state of said second circuit means in response to each of said second timing pulses.

Claim 7

The circuit for decoding data represented by two different frequencies in an input signal, said circuit comprising: means responsive to the frequencies of said input signal for providing a signal having various phase differences with said input signal, each of said phase differences occurring in response to a different one of said input signal frequencies means for detecting each of said phase differences; said input signals occurring at two different frequencies; said frequency-responsive means providing a signal which leads said input signal when said input signal is at one of said two frequencies and lags said input signal when said input signal is at the other of said two frequencies; said detecting means providing an output signal indicative of whether the signal from said frequency-responsive means lags or leads said input signal; said detecting means being adapted to receive said input signal and the signal from said frequency-responsive means, said input signal and said signal from said frequency-responsive means each comprising a series of digital pulses when received by said detecting means, each of the pulses of the latter signal corresponding to one of the pulses in said input signal and being received by said detecting means concurrently with part of its corresponding pulse in said input signal; said detecting means comprising: first circuit means for receiving said input signal and the signal from said frequency-responsive means, said first circuit means being bistable for a first period of time after receiving the leading edges of the pulses in the lagging one of said signals, the state of said first circuit during said first periods being dependent on which of said signals is leading; and means for providing an output signal indicative of the state of said first circuit means during said first periods.

Claim 8

The circuit for decoding data represented by two different frequencies in an input signal, said circuit comprising: means responsive to the frequencies of said input signal for providing a signal having various phase differences with said input signal, each of said phase differences occurring in response to a different one of said input signal frequencies means for detecting each of said phase differences; said input signals occurring at two different frequencies; said frequency-responsive means providing a signal which leads said input signal when said input signal is at one of said two frequencies and lags said input signal when said input signal is at the other of said two frequencies; said detecting means providing an output signal indicative of whether the signal from said frequency-responsive means lags or leads said input signal; said detecting means being adapted to receive said input signal and the signal from said frequency-responsive means, said input signal and said signal from said frequency-responsive means each comprising a series of digital pulses when received by said detecting means, each of the pulses of the latter signal corresponding to one of the pulses in said input signal and being received by said detecting means concurrently with part of its corresponding pulse in said input signal; said detecting means comprising: first circuit means for receiving said input signal and the signal from said frequency-responsive means, said first circuit means being bistable for a first period of time after receiving the leading edges of the pulses in the lagging one of said signals, the state of said first circuit during said first periods being dependent on which of said signals is leading; and means for providing an output signal indicative of the state of said first circuit means during said first periods.

Claim 9

The circuit as recited in claim 5 wherein said first circuit means is bistable for each period beginning when it receives the leading edge of one of the pulses in the lagging one of said signals and ending when it receives the lagging edge of the corresponding pulse in the leading one of said signals.

Claim 10

The circuit as recited in claim 5 wherein said output signal providing means comprises: a. means for providing first timing pulses in response to the leading edges of the pulses in the lagging one of said signals; and b. bistable circuit means adapted to respond to the state of said first circuit means in response to each of said first timing pulses.

Claim 11

The circuit as recited in claim 5 wherein said detecting means comprises: a. second circuit means for receiving said input signal and the signal from said frequency-responsive means, said second circuit means being bistable for second periods of time after receiving the lagging edges of the pulses in the lagging one of said signals, the state of said second circuit means during said second periods being dependent on which of said signals is leading; and b. means for providing an output signal indicative of the state of said second circuit means during said second periods.

Claim 12

The circuit as recited in claim 8 wherein said second circuit means is bistable for each period beginning when it receives the lagging edge of one of the pulses in the leading one of said signal and ending when it receives the leading edge of the next pulse received in either of said signals.

Claim 13

The circuit as recited in claim 8 wherein said output signal providing means comprises: a. means for providing second timing pulses in response to the lagging edges of the pulses in the lagging one of said signals; and b. bistable circuit means adapted to respond to the state of said second circuit means in responses to each of said first timing pulses.

Claim 14

The circuit as recited in claim 5 wherein said detecting means comprises: a. first circuit means For receiving said input signal and the signal from said frequency-responsive means, said first circuit means being bistable for first periods of time after receiving the leading edges of the pulses in the lagging one of said signals, the state of said first circuit means during said first periods being dependent on which of said signals is leading; b. second circuit means for receiving said input signal and the signal from said frequency-responsive means, said second circuit means being bistable for second periods of time after receiving the lagging edges of the pulses in the lagging one of said signals, the state of said second circuit means during said second periods being dependent on which of said signals is leading; and c. means for providing an output signal indicative of the state of said first circuit means during said first periods and of the state of said second means during said second periods.

Claim 15

The circuits as recited in claim 11 wherein said output signal providing means comprises: a. means for providing first timing pulses in response to the leading edges of the pulses in the lagging one of said signals; b. means for providing second timing pulses in response to the lagging edges of the pulses in the laggine one of said signal; and c. bistable circuit means adapted to respond to the state of said first circuit means in response to each of said first timing pulses, said bistable circuit means also adapted to respond to the state of said second circuit means in response to each of said second timing pulses.

Claim 16

The circuits as recited in claim 12 wherein said first and second timing pulses occur in an alternating sequence.

Claim 17

A circuit for decoding data represented by two different frequencies in an input signal, said circuit comprising: means responsive to the frequency of said input signal for generating a signal corresponding pulse to pulse to said input signal, the leading edge of a pulse of said generated signal leading the corresponding pulse of said input signal when said input signal is at one of said two frequencies, the leading edge of a pulse of said generated signal lagging behind the corresponding pulse of said input signal when said input signal is at the other of said two frequencies; means for detecting the phase differences between corresponding pulses of said input signal and said generated signal, said frequency-responsive means including an operational amplifier having an inverting input and a non-inverting input, said input signal being applied to said non-inverting input.

Claim 18

A circuit for decoding data represented by two different frequencies in an input signal, said circuit comprising: means responsive to the frequency of said input signal for generating a signal corresponding pulse to pulse to said input signal, the leading edge of a pulse of said generated signal leading the corresponding pulse of said input signal when said input signal is at one of said two frequencies, the leading edge of a pulse of said generated signal lagging behind the corresponding pulse of said input signal when said input signal is at the other of said two frequencies; means for detecting the phase differences between corresponding pulses of said input signal and said generated signal, said frequency-responsive means including an operational amplifier having an inverting input and a non-inverting input, said input signal being applied to said non-inverting input.

Claim 19

A circuit for decoding data represented by two different frequencies in an input signal, said circuit comprising: means responsive to the frequency of said input signal for generating a signal corresponding pulse to pulse to said input signal, the leading edge of a pulse of said generated signal leading the corresponding pulse of said input signal when said input signal is at one of said two frequencies, the leading edge of a pulse of said generated signal lagging behind the corresponding pulse of said input signal when said input signal is at the other of said two frequencies; means for detecting the phase differences between corresponding pulses of said input signal and said generated signal, said detecting means including first circuit means for receiving said input signal and said generated signal, said first circuit means being bistable for first periods of time while receiving said signals, the state of said first circuit during said first periods being dependent on which of said signals is leading; second circuit means for receiving said input signal and said generated signal, said second circuit means being bistable for second periods of time while receiving said signals, the state of said second circuit means being dependent on which of said signals is leading; and means for providing an output signal indicative of the state of said first circuit means during said first periods and of the state of said seCond circuit means during said second periods.

Claim 20

A circuit for decoding data represented by two different frequencies in an input signal, said circuit comprising: means responsive to the frequency of said input signal for generating a signal corresponding pulse to pulse to said input signal, the leading edge of a pulse of said generated signal leading the corresponding pulse of said input signal when said input signal is at one of said two frequencies, the leading edge of a pulse of said generated signal lagging behind the corresponding pulse of said input signal when said input signal is at the other of said two frequencies; means for detecting the phase differences between corresponding pulses of said input signal and said generated signal, said detecting means including first circuit means for receiving said input signal and said generated signal, said first circuit means being bistable for first periods of time while receiving said signals, the state of said first circuit during said first periods being dependent on which of said signals is leading; second circuit means for receiving said input signal and said generated signal, said second circuit means being bistable for second periods of time while receiving said signals, the state of said second circuit means being dependent on which of said signals is leading; and means for providing an output signal indicative of the state of said first circuit means during said first periods and of the state of said seCond circuit means during said second periods.

Claim 21

In a circuit for demodulating an input signal modulated between first and second predetermined frequencies, the combination comprising: means for splitting said input signal into two bipolar square wave signals having the same frequency as said input signal, each polarity reversal in one of said signals being coincident with a corresponding polarity reversal occurring in the other of said signals; phase shifting means constructed and arranged to shift the phase of one of said square wave signals with respect to the other to produce a shifted square wave signal, said phase shift being such that when said signals occur at said first predetermined frequency the shifted signal leads the nonshifted signal and when said signals occur at the second predetermined frequency the shifted signal lags the nonshifted signal; and phase detection means for comparing the time of occurrence of each polarity reversal contained in said shifted signal with respect to the time of occurrence of the corresponding polarity reversal in said nonshifted signal and for generating a bistable output signal having a first state when the polarity reversals in said shifted signal lead the corresponding polarity reversals in said nonshifted signal and having a second state when the polarity reversals in said shifted signal lag the corresponding polarity reversals in said nonshifted signal.

Claim 22

In a circuit for demodulating an input signal modulated between first and second predetermined frequencies, the combination comprising: means for splitting said input signal into two bipolar square wave signals having the same frequency as said input signal, each polarity reversal in one of said signals being coincident with a corresponding polarity reversal occurring in the other of said signals; phase shifting means constructed and arranged to shift the phase of one of said square wave signals with respect to the other to produce a shifted square wave signal, said phase shift being such that when said signals occur at said first predetermined frequency the shifted signal leads the nonshifted signal and when said signals occur at the second predetermined frequency the shifted signal lags the nonshifted signal; and phase detection means for comparing the time of occurrence of each polarity reversal contained in said shifted signal with respect to the time of occurrence of the corresponding polarity reversal in said nonshifted signal and for generating a bistable output signal having a first state when the polarity reversals in said shifted signal lead the corresponding polarity reversals in said nonshifted signal and having a second state when the polarity reversals in said shifted signal lag the corresponding polarity reversals in said nonshifted signal.

Claim 23

The demodulating circuit set forth in claim 27, wherein said phase detection means further comprises: sampling circuit means responsive to said shifted and nonshifted signals for generating a sampling pulse each time said two signals assume the same polarity state; first bistable circuit means operable in response to each corresponding pair of positive polarity reversals occurring in said shifted and non-shifted signals to generate a first bistable output signal representative of the signal containing the leading positive polarity reversal; second bistable circuit means operable in response to each corresponding pair of negative polarity reversals occurring in said shifted and nonshifted signals to generate a second bistable output signal representative of the signal containing the leading negative polarity reversal; and output circuit means responsive to each said sampling pulse to generate a final bistable output signal alternately representative of the states of the first and second bistable output signals.