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Semiconductor device and method of manufacturing the device

Assignee: US Philips Corp
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Filing: 1971-02-04
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Granted: 1973-06-12
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Expires: 1991-02-04
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Abstract

Abstract A semiconductor device having a planar structure, in particular a transistor, having at least an emitter zone which is provided with a series resistance in the form of a resistance layer provided on the surface, the resistance layer being also provided elsewhere on the device for a completely different purpose, where it is entirely covered by a metal layer. Application in particular for protection of the emitter-base junction in washedout emitters in silicon transistors in which the resistance layer consists of titanium and the metallization consists of alunimium.

Inventors

  • 👤 G Kerr

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 17:27
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/121; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10P; H10P95/00; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484; H10W72/00; H10W72/90

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 39 words
A device as set forth in claim 1 wherein the semiconductor is of silicon, the insulating layer is of silicon oxide, the resistance layer is of titanium, and the metallization is of aluminum and the metal layer of gold.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-06-11 1976-12-11 1977-06-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-06-11 1980-12-11 1981-06-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-06-11 1984-12-11 1985-06-12 $7700.00 Window Closed / Lapsed

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