Static bipolar to mos interface circuit

Claim 1

In a ratio inverter circuit comprising a first field effect transistor and a first resistive element connected in series between means for connection across a potential supply having first and second terminals at first and second potential levels, respectively, the end of said first resistive element remote from said first transistor being connected to said means for connection to said first terminal, the gate electrode of said first transistor being connected to means for connection to an input signal supply swinging between first and second voltage levels, said first voltage level being of such magnitude as to turn said first transistor hard on and said second voltage being of such magnitude that the conductance of said first transistor when said second voltage is applied at the gate electrode thereof is substantially less than with said first voltage applied thereto, and the drain electrode of said transistor being connected to means for connection to means for deriving an output potential therefrom, the improvement which comprises bias means for providing a bias at the source electrode of said first transistor when said second voltage level is applied at the gate electrode thereof which modifies the effective turn-on voltage of said transistor to a value such that the conductance of said transistor is substantially zero with said second voltage applied thereto and said bias means providing substantially a short-circuit between said source electrode of said first transistor and said means for connection to said second terminal of said potential supply when said first voltage level signal is applied at the gate electrode of said first transistor, said bias means comprising a second field-effect transistor connected between the source electrode of said first transistor and said means for connection to said second terminal means and also connected in series with a second resistive element to constitute a second ratio inverter circuit, the end of said second resistive element remote from said second transistor being connected to means for connection to a reference ground potential point, the source electrode of said second transistor being connected to said means for connection to said second terminal of said potential supPly, the drain electrode of said second transistor being connected to the source electrode of said first transistor and to one end of said second resistive element, and the gate electrode of said second transistor being connected to the gate electrode of said first transistor, the conductance of said second transistor being high during application to the gate electrode thereof of said first voltage level input signal, whereby bias at the source electrode of said first transistor is at substantially the value of said second potential level of said power supply, thereby permitting said first transistor to turn hard on during application to the gate electrode thereof of said first voltage level input signal, the conductance of said second transistor being relatively low during application to the gate electrode thereof of said second voltage level input signal, whereby significant bias is applied to the source electrode of said first transistor thereby modifying the effective turn-on potential of said first transistor to a value such that the conductance of said first transistor when said second input voltage is applied at the gate thereof is substantially zero, the resistive values of said second transistor and said second resistive element being such as to form a potential divider whereby the required bias potentials are applied to the source electrode of said first transistor as aforesaid.