Encoder for high-speed pcm system

Claim 1

An encoder for converting an analog signal into a code word of n+m bits identifying one of 2n amplitude ranges and one of 2m amplitude levels within each range, comprising a group of 2n comparison stages each assigned to a respective amplitude range; a set of 2m comparators in each of said stages, each comparator having a first and a second input; feed means for supplying an analog signal to all said firsT inputs in parallel; biasing means for applying respective reference potentials to said second inputs, said potentials being of progressively higher magnitudes corresponding to the 2n m amplitude levels encompassed by said 2n ranges, each comparator generating a finite output upon the magnitude of said analog signal at least equaling the reference potential applied to its second input; logical circuitry connected to said comparators for converting said finite outputs thereof into a first combination of n bits, indicating the highest-ranking comparison stage in which a finite output is generated, and a second combination of m bits, indicating the highest-ranking comparator generating such finite output in the indicated stage; an individual flip-flop inserted between each comparator and said logical circuitry for temporarily storing the output of the associated comparator; and timer means for periodically resetting said flip-flops; said logical circuitry including gating means connected to receive the outputs of the comparators of every comparison stage except the lowest-ranking one, the lowest-ranking comparator of every comparison stage except the lowest-ranking stage being connected to said gating means of the next lower stage for blocking same in the presence of a finite output of said lowest-ranking comparator; said gating means including 2m-1 OR gates, each with 2n inputs connected to like-ranking comparators of all said stages other than the lowest-ranking comparators, a first gating matrix connected to receive the outputs of said lowest-ranking comparators for deriving therefrom said first combination of n bits, and a second gating matrix connected to receive the outputs of all said OR gates for deriving therefrom said second combination of m bits.