US3737890A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Character to dot generator
Assignee: Motorola Solutions Inc
•
Filing: 1970-08-24
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Granted: 1973-06-05
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Expires: 1990-08-24
Abstract
Abstract An apparatus for converting binary signals representing characters to dot matrix signals representing the characters and transmitting the dot matrix signals in a particular sequence. A plurality of binary signals representing a predetermined number of alpha-numeric characters are coupled to a first memory and recirculated through the memory in a predetermined sequence. A dot translator coupled to the memory output converts the binary signals to dot matrix signals representing the character. A dot sampler selects particular of the dot matrix signals and couples them to a modulator for phase modulating an output signal. A second storage memory identical to the first storage memory can be used to store a second group of binary signals while the binary signals in the first group are being recirculated.
Inventors
- 👤 R Salava
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:14
CPC Classifications
H; H03; H03M; H03M5/00
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
225 words
An apparatus for converting binary signals representing characters to dot matrix signals representing such characters including in combination; memory means for receiving said binary signals, said memory means including first storage means for serially storing and recirculating said binary signals, said first storage means having an input and an output, binary signal control means coupled to said input and said output of said first storage means, said binary signal control means being operative to receive and couple a predetermined number of said binary signals to said first storage means input, and to couple said first storage means output to said first storage means input to form a first storage means loop after said predetermined number of binary signals have been coupled to said first storage means, function means coupled to said memory means and operative to cause said first storage means to serially enter said binary signals therein and serially recirculate said binary signals from output to input through said storage means loop in said predetermined sequence, dot utilization means coupled to said memory means, said dot utilization means being responsive to said binary signals coupled thereto to develop dot matrix signals and couple said dot matrix signals therefrom, said function means being coupled to said dot utilization means and operative to cause particular dot matrix signals to be coupled from said dot utilization means.
Claim 2
Independent Claim
225 words
An apparatus for converting binary signals representing characters to dot matrix signals representing such characters including in combination; memory means for receiving said binary signals, said memory means including first storage means for serially storing and recirculating said binary signals, said first storage means having an input and an output, binary signal control means coupled to said input and said output of said first storage means, said binary signal control means being operative to receive and couple a predetermined number of said binary signals to said first storage means input, and to couple said first storage means output to said first storage means input to form a first storage means loop after said predetermined number of binary signals have been coupled to said first storage means, function means coupled to said memory means and operative to cause said first storage means to serially enter said binary signals therein and serially recirculate said binary signals from output to input through said storage means loop in said predetermined sequence, dot utilization means coupled to said memory means, said dot utilization means being responsive to said binary signals coupled thereto to develop dot matrix signals and couple said dot matrix signals therefrom, said function means being coupled to said dot utilization means and operative to cause particular dot matrix signals to be coupled from said dot utilization means.
Claim 3
Dependent Claim
53 words
The apparatus of claim 1 further including, signal generation means for generating an output signal, modulation means for modulating said output signal coupled to said signal generation means, said modulation means being coupled to said dot utilization means and responsive to said particular dot matrix signals coupled thereto to modulate said output signal.
Claim 4
Dependent Claim
154 words
The apparatus of claim 1 further including, second storage means for storing and recirculating said binary signals, said second storage means having an input and an output, said binary signal control means coupled to said input and said output of said second storage means, said binary signal control means being operative to receive and couple a predetermined number of said binary signals to said second storage means input, said binary signal control means further operative to couple said second storage means output to said second storage means input to form a second storage means loop after said predetermined number of binary signals have been coupled to said second storage means, said function means being coupled to said second storage means and operative to cause said second storage means to serially enter said binary signals therein and serially recirculate said binary signals from output to input through said storage means loop in said predetermined sequence.
Claim 5
Dependent Claim
173 words
The apparatus of claim 3 wherein said function means includes, continuously operable signal generation means for developing first signals, means coupling said first signals to said first and second storage means, said first and second storage means being operative in response thereto to enter said binary signals therein, resetable second counter means coupled to said signal generation means and operative in response thereto to count to a particular number, said resetable second counter means developing second counting signals in response to each count, means for generating variable length pulse trains in response to particular of said second counting signals coupled to said resetable counter means, means for coupling said variable length pulse trains to said first and second storage means for recirculaTing said binary signals from output to input through said storage means loops in said predetermined sequence, and means coupling said second counting signals to said dot utilization means, said dot utilization means being operative in response to said second counting signals to couple particular ones of said dot matrix signals therefrom.
Claim 6
Dependent Claim
262 words
The apparatus of claim 3 wherein said binary signal control means includes, input means for receiving said binary signals, first switch means having a first and second state, said first switch means being coupled to said storage means input and output and to said input means, said first switch means when in said first state being operative to couple said binary signals from said input means to said first storage means, said first switch means when in said second state being operative to couple said first storage means output to said first storage means input to form said first storage means loop, second switch means having a first and second state, said second switch means being coupled to said second storage means input and output and to said input means, said second switch means when in said first state being operative to couple said binary signals from said input means to said second storage means, said second switch means when in said second state being operative to couple said second storage means output to said second storage means input to form said second storage means loop, said second switch means being in said second state when said first switch means is in said first state, and said second switch means being in said first state when said first switch means is in said second state, whereby one of said first and second storage means is entering said predetermined number of binary signals therein while the other of said first and second storage means recirculates said binary signals therein in said predetermined sequence.
Claim 7
Dependent Claim
73 words
The apparatus of claim 5 further including, circuit means coupled to said input means, said first and second switch means, and said function means, said circuit means being operative in response to receipt of said predetermined number of binary signals by said input means and the termination of the recirculation of said binary signals in said predetermined sequence by said function means to cause said first and second switch means to switch states.
Claim 8
Dependent Claim
192 words
The apparatus of claim 6 wherein said circuit means includes, resetable first counter means coupled to said input means for counting said predetermined number of binary signals and developing first counting signals in response thereto, AND gate means coupled to said counter means and said function means, said AND gate means being operative in response to said first counting signal representing the last of said predetermined number of binary signals, and the completion of recirculation of said binary signals in said predetermined sequence in one of said first and second storage means by said function means, to develop an AND gate signal, first circuit means coupled to said AND gate means and said first and second switching means, said first circuit means being operative in response to said AND gate signal to develop a first circuit signal, said first and second switch means being operative in response to said first circuit signal to switch states, reset means coupled to said AND gate means and operative in response to said AND gate signal to develop a reset signal, means coupling said reset signal to said first counter means for reseting said first counter.
Claim 9
Dependent Claim
228 words
The apparatus of claim 6 wherein said function means includes, oscillator means for generating a reference frequency, divider circuit means coupled to said oscillator means for dividing said reference frequency to obtain first, second, third and fourth frequency signals therefrom, said first signal being lower in frequency than said second signal, said second signal being lower in frequency than said third signal, and said third signal being lower in frequency than said fourth sigNal, means coupling said first signal to said first and second storage means, said storage means being operative in response to said first signal to enter said binary signals in said storage means, resetable second counter means coupled to said divider circuit means and operative in response to said second signals to count to a particular number, said second counter means developing second counting signals for each count, second circuit means coupled to said divider means and said second counter means, said second circuit means being operative in response to particular of said second counting signals and said fourth signals to develop variable length pulse trains, and means coupling said second circuit means to said first and second storage means, said first and second storage means being operative in response to said variable length pulse trains to recirculate said binary signals from said output to input through said storage means loops in said predetermined sequence.
Claim 10
Dependent Claim
81 words
The apparatus of claim 7 wherein said dot utilization means includes, dot translator means coupled to said first storage means output and said second storage means output, said dot translator means being operative in response to binary signals coupled thereto to develop dot matrix signals representing said characters, dot sampler means coupled to said dot translator means and said function means, said function means being operative to cause said particular dot matrix signals to be coupled from said dot sampler means.
Claim 11
Dependent Claim
357 words
The apparatus of claim 9 wherein said function means includes, oscillator means for developing a reference frequency, divider circuit means coupled to said oscillator means for dividing said reference frequency to obtain first, second, third and fourth frequency signals, said first signal being lower in frequency than said second signal, said second signal being lower in frequency than said third signal, and said third signal being lower in frequency than said fourth signal, means coupling said first signal to said first and second storage means, said storage means being responsive to said first signals to enter said binary signals in said storage means, resetable second counter means coupled to said divider circuit means and operative in response to said second signals to count to a particular number, said second counter means developing second counting signals in response to each count, second circuit means coupled to said divider circuit means and said second counter means, said second circuit means being operative in response to said fourth signals and particular of said second counting signals to develop variable length trains of pulses, third switch means, having a first and second state coupled to said second circuit means and said first and second storage means, means coupling said first signal from said divider circuit means to said third switch means, said third switch means being in said first state when said first switch means is in said first state, said third switch means when in said first state being operative to couple said first signals to said first storage means and said variable length pulse trains from said second circuit means to said second storage means, said third switch means when in said second state being operative to couple said first signals to said second storage means and said variable length pulse trains from said second circuit means to said first storage means, said third switch means being further coupled to said first circuit means and operative in response to said first circuit signals to switch states, said second counter means coupled to said reset means and operative in response to said reset signal to reset said second counter means.
Claim 12
Dependent Claim
55 words
The apparatus of claim 10 further including, modulator means coupled to said dot sampler means and said divider circuit means, means coupling said third signals from said divider circuit means to said modulator means, said modulator means operative in response to said dot matrix signals coupled theReto to shift the phase of said third signals.
Claim 13
Dependent Claim
64 words
The apparatus of claim 10 wherein said means coupling said first signal from said divider circuit means to said third switch means includes, fourth switch means coupled to said divider circuit means, said third switch means and said first counter means, said fourth switch means operative in response to the said first counter signals to couple said first signals to said third switch means.
Claim 14
Dependent Claim
24 words
The apparatus of claim 10 wherein said divider circuit means includes, a plurality of frequency divider circuits serially connected for dividing said reference frequency.
Claim 15
Dependent Claim
23 words
The apparatus of claim 10 wherein said second counter means includes a plurality of counters serially connected to count to said particular number.
Claim 16
Dependent Claim
13 words
The apparatus of claim 14 wherein said plurality of counters is four counters.
Claim 17
Dependent Claim
11 words
The apparatus of claim 15 wherein said particular number is 2,880.
Claim 18
Dependent Claim
83 words
The apparatus of claim 10 wherein said second circuit means includes, logic circuit means coupled to said second counter means, said logic circuit means operative in response to particular of said second counting signals coupled thereto to develop logic signals, a variable radix counter coupled to said logic circuit means, said third switch means, and said divider circuit means, said variable radix counter operative in response to each of said logic signals to develop a train of pulses each having a particular length.
Claim 19
Independent Claim
333 words
An apparatus for converting binary signals representing characters to dot matrix signals representing such characters including in combination, first storage means for storing and serially shifting said binary signals, said first storage means having an input and an output, binary signal control means coupled to said first storage means input and output, said binary signal control means being operative to receive and couple a predetermined number of said binary signals to said first storage means input and to develop first counting signals in response to said predetermined number of binary signals, said binary signal control means being further operative to couple said first storage means output to said first storage means input to form a first storage means loop after said predetermined number of binary signals have been coupled to said first storage means, function control means coupled to said binary control means and to said first storage means, said function control means being operative in response to said first counting signals to develop first pulses and to couple the same to said first storage means, said first storage means being operative in response to said first pulses to serially couple said binary signals into said first storage means, said function control means including means operating continuously to count to a particular number and develop second counting signals in response thereto, said function control means developing variable length trains of pulses in response to particular ones of said second counting signals, said first storage means being operative in response to said variable length trains of pulses to serially recirculate said binary signals from said output of said first storage means through said first storage means loop, and dot utilization means coupled to said first storage means output and said function control means, said dot utilization means being responsive to the binary signals coupled thereto to develop dot matrix signals, said dot utilization means being further responsive to particular ones of said second counting signals coupled thereto to couple particular dot matrix signals therefrom.
Claim 20
Independent Claim
333 words
An apparatus for converting binary signals representing characters to dot matrix signals representing such characters including in combination, first storage means for storing and serially shifting said binary signals, said first storage means having an input and an output, binary signal control means coupled to said first storage means input and output, said binary signal control means being operative to receive and couple a predetermined number of said binary signals to said first storage means input and to develop first counting signals in response to said predetermined number of binary signals, said binary signal control means being further operative to couple said first storage means output to said first storage means input to form a first storage means loop after said predetermined number of binary signals have been coupled to said first storage means, function control means coupled to said binary control means and to said first storage means, said function control means being operative in response to said first counting signals to develop first pulses and to couple the same to said first storage means, said first storage means being operative in response to said first pulses to serially couple said binary signals into said first storage means, said function control means including means operating continuously to count to a particular number and develop second counting signals in response thereto, said function control means developing variable length trains of pulses in response to particular ones of said second counting signals, said first storage means being operative in response to said variable length trains of pulses to serially recirculate said binary signals from said output of said first storage means through said first storage means loop, and dot utilization means coupled to said first storage means output and said function control means, said dot utilization means being responsive to the binary signals coupled thereto to develop dot matrix signals, said dot utilization means being further responsive to particular ones of said second counting signals coupled thereto to couple particular dot matrix signals therefrom.
Claim 21
Dependent Claim
296 words
The apparatus of claim 18 further including second storage means for storing and serially shifting said binary signals, said second storage means having an input and an output, said binary signal control means coupled to said second storage means input and output and operative to couple a predetermined number of said binary signals to said second storage means input when said first Storage means output is coupled to said first storage means input forming said first storage means loop, said binary signal control means developing first counting signals in response to said predetermined number of binary signals coupled to said second storage means, said binary signal control means further operative to couple said second storage means output to said second storage input to form a second storage means loop after said predetermined number of binary signals have been coupled to said second storage means, and during the time that said binary signal control means is operative to couple a predetermined number of said binary signals to said first storage means input, said function control means operative in response to said first counting signals coupled thereto to couple said first pulses to said second storage means, said second storage means operative in response to said first pulses to serially couple said binary signals into said second storage means, and second storage means further operative in response to said variable length trains of pulses to serially recirculate said binary signals therethrough from output to input of said second storage means through said storage means loop, said dot utilization means responsive to the binary signals coupled thereto from said second storage means to develop dot matrix signals, said dot utilization means further responsive to particular of said second counting signals coupled thereto to couple particular dot matrix signals therefrom.
Claim 22
Independent Claim
633 words
An apparatus for converting binary signals representing characters to dot matrix signals representing said characters including in combination, input means for receiving said binary signals, a first storage circuit for serially storing said binary signals, said first storage circuit having an input and an output, a first switching circuit having a first state and a second state, said first switching circuit being coupled to said input means, said first storage circuit input and said first storage circuit output, said first switching circuit when in said first state coupling said input means to said first storage means input, a dot translator circuit coupled to said first storage means output for developing dot matrix signals in response to said binary signals coupled thereto, a dot sampler circuit coupled to said dot translator circuit for selecting particular ones of said dot matrix signals, a resetable counter circuit coupled to said input means for counting said binary signals, said counter circuit operating to count to a first particular number and developing first counting signals in response to each count, a control circuit including a first portion operating continuously to develop first pulses, first circuit means having an output, and an input coupled to said counter circuit and control circuit, said first circuit operative in response to the combination of the first counting signals and the first pulses coupled thereto to couple said first pulses to said output, a second switching circuit having a first and a second state coupled between said first circuit means output and said first storage circuit, said second switching circuit when in said first state coupling said first pulses to said first storage circuit, said first and second switching circuits being concurrently in one of said first and second states, said first storage circuit being responsive to said first pulses to serially shift said binary signals through said first storage circuit from input to output, said control circuit further including a resetable second portion operating continuously to count to a second particular number, said second portion developing second counting signals in response to each count, second circuit means coupled to said counter circuit and said control circuit second portion, said second circuit means responsive to the combination of siad first counting signal representing said first particular number and the second counting signal representing said second particular number to develOp a second circuit signal, means coupling said second circuit signal to said first switching circuit and said second switching circuit, said first switching circuit operative in response to said second circuit signal to switch states, said first switching circuit when in said second state coupling said storage means output to said storage means input forming a first storage circuit loop, said second switching circuit operative in response to said second circuit signal to switch states means further coupling said second circuit signal to said counter circuit and said control circuit second portion, said counter circuit and control circuit second portion operative in response to said second circuit signal to reset said first and second counts, said control circuit further including a third portion for developing a variable length train of pulses in response to particular of said second portion counting signals, means coupling said control circuit third portion to said second switching circuit, said second switching circuit when in said second state operative to couple said variable length train of pulses to said first storage means, said first storage means responsive to said variable length train of pulses to serially shift said binary signals through said first storage circuit from output to input through said first storage circuit loop, and means coupling said second counting signals to said dot sampler circuit, said dot sampler circuit being operative in response to said second counting signals to couple particular ones of said dot matrix signals therefrom.
Claim 23
Independent Claim
633 words
An apparatus for converting binary signals representing characters to dot matrix signals representing said characters including in combination, input means for receiving said binary signals, a first storage circuit for serially storing said binary signals, said first storage circuit having an input and an output, a first switching circuit having a first state and a second state, said first switching circuit being coupled to said input means, said first storage circuit input and said first storage circuit output, said first switching circuit when in said first state coupling said input means to said first storage means input, a dot translator circuit coupled to said first storage means output for developing dot matrix signals in response to said binary signals coupled thereto, a dot sampler circuit coupled to said dot translator circuit for selecting particular ones of said dot matrix signals, a resetable counter circuit coupled to said input means for counting said binary signals, said counter circuit operating to count to a first particular number and developing first counting signals in response to each count, a control circuit including a first portion operating continuously to develop first pulses, first circuit means having an output, and an input coupled to said counter circuit and control circuit, said first circuit operative in response to the combination of the first counting signals and the first pulses coupled thereto to couple said first pulses to said output, a second switching circuit having a first and a second state coupled between said first circuit means output and said first storage circuit, said second switching circuit when in said first state coupling said first pulses to said first storage circuit, said first and second switching circuits being concurrently in one of said first and second states, said first storage circuit being responsive to said first pulses to serially shift said binary signals through said first storage circuit from input to output, said control circuit further including a resetable second portion operating continuously to count to a second particular number, said second portion developing second counting signals in response to each count, second circuit means coupled to said counter circuit and said control circuit second portion, said second circuit means responsive to the combination of siad first counting signal representing said first particular number and the second counting signal representing said second particular number to develOp a second circuit signal, means coupling said second circuit signal to said first switching circuit and said second switching circuit, said first switching circuit operative in response to said second circuit signal to switch states, said first switching circuit when in said second state coupling said storage means output to said storage means input forming a first storage circuit loop, said second switching circuit operative in response to said second circuit signal to switch states means further coupling said second circuit signal to said counter circuit and said control circuit second portion, said counter circuit and control circuit second portion operative in response to said second circuit signal to reset said first and second counts, said control circuit further including a third portion for developing a variable length train of pulses in response to particular of said second portion counting signals, means coupling said control circuit third portion to said second switching circuit, said second switching circuit when in said second state operative to couple said variable length train of pulses to said first storage means, said first storage means responsive to said variable length train of pulses to serially shift said binary signals through said first storage circuit from output to input through said first storage circuit loop, and means coupling said second counting signals to said dot sampler circuit, said dot sampler circuit being operative in response to said second counting signals to couple particular ones of said dot matrix signals therefrom.
Claim 24
Dependent Claim
305 words
The apparatus of claim 20 further including, a second storage circuit for serially storing said binary signals, said second storage circuit having an input and an output, a third switching circuit having a first and second state, said third switching circuit being coupled to said input means, said second storage circuit input and said second storage circuit output, said third switching circuit when in said first state coupling said input means to said second storage circuit input, said third switching circuit being in said first state when said first and second switching circuits are in said second state, said dot translator circuit coupled to said second storage means output for developing dot matrix signals in response to said binary signals coupled thereto, means coupling said second circuit signals to said third switching circuit, said third switching circuit operative in response to said second circuit signals to switch states, said third switching circuit when in said second state coupling said second storage means output to said second storage means input to form a second storage means loop; said third switching circuit being in said second state when said first and second switching circuits are in said first states, means coupling said second switching means to said second storage circuit, said second switching means when in said first state coupling said variable length trains of pulses to said second storage means, said second storage means operative in response to said variable length trains of pulses to serially shift said binary signals through said second circuit from output to input through said second storage circuit loop, said second switching means when in said second state coupling said first pulses to said second storage circuit, said second storage circuit responsive to said first pulses to serially shift said binary signals through said second storage circuit from input to output.
Claim 25
Dependent Claim
29 words
The apparatus of claim 21 wherein said first storage circuit includes a plurality of storage registers coupled in parallel between said first switching means and said dot translator means.
Claim 26
Dependent Claim
15 words
The apparatus of claim 22 wherein said plurality of storage registers includes six storage registers.
Claim 27
Dependent Claim
28 words
The apparatus of claim 21 wherein said second storage circuit includes a plurality of storage registers coupled in parallel between said second switching means and said translator means.
Claim 28
Dependent Claim
15 words
The apparatus of claim 24 wherein said plurality of storage registers includes six storage registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |