Narrow band digital filter

Claim 2

A narrow band digital filter comprising: digital filter means (3); means (1) for applying digital sequences to the filter means at a digit rate F; and means (5, 7) for sampling the digital filter means output sequence responsive to the associated input sequence at a frequency Fi and for recirculating the output sequence and reapplying it to the filter, there being N such successive recirculations, the sampling frequency for the ith circulation being Fi F/ni where i 1, 2, 3, . . . N, and n being any positive real integer.

Claim 3

A narrow band digital filter according to claim 1, wherein the digital sequences first applied to the filter means input represent analog signals sampled at twice the Nyquist rate; n being equal to two.

Claim 4

A narrow band digital filter comprising: digital filter means (FIG. 4) including: a Read Only Memory (ROM); first (L1) and second (L2) delay elements; a logic arrangement (OR, ACCU) for addressing the Read Only Memory at locations determined by the contents of either the first or second delay elements and for serially reading out the memory address contents; means (1) for applying digital sequences to the first delay element at digit rate F; means (D, 5, 7) for sampling the serially read out memory contents at a frequency Fi and for applying said sampled digital sequence to the second delay element, there being N samplings, the sampling frequency Fi at the ith sampling being Fi F/ni, 1, 2, . . . N, and n being an arbitrary real positive integer, each sampled sequence being applied to the second delay element further being displaced D seconds from the application of digits into the first delay element, the interval D being sufficien to avoid overlap.

Claim 5

A narrow band digital filter comprising: digital filter means (FIG. 4) including: a Read Only Memory (ROM); first (L1) and second (L2) delay elements; a logic arrangement (OR, ACCU) for addressing the Read Only Memory at locations determined by the contents of either the first or second delay elements and for serially reading out the memory address contents; means (1) for applying digital sequences to the first delay element at digit rate F; means (D, 5, 7) for sampling the serially read out memory contents at a frequency Fi and for applying said sampled digital sequence to the second delay element, there being N samplings, the sampling frequency Fi at the ith sampling being Fi F/ni, 1, 2, . . . N, and n being an arbitrary real positive integer, each sampled sequence being applied to the second delay element further being displaced D seconds from the application of digits into the first delay element, the interval D being sufficien to avoid overlap.