Method of manufacturing an integrated circuit having a transistor isolated by the collector region

Claim 1

A method for manufacturing a semiconductor integrated circuit means having at least one transistor portion and two diode portions comprising the steps of: preparing a semiconductor substrate of first conductivity type having one principal surface in which first, second and third regions of second conductivity type extend; growing epitaxially a semiconductor layer of first conductivity type having a relatively low impurity concentration to cover said first to third regions of second conductivity type; diffusing the impurity determining the second conductivity type around said first to third regions and forming fourth, fifth and sixth regions of second conductivity type like a closed ring from the surface of said semiconductor layer towards said first to third regions thereunder, thereby surrounding and electrically isolating first, second and third portions of said semiconductor layer of first conductivity type; diffusing the impurity determining the first conductivity type and forming first and second regions of first conductivity type having a relatively high impurity concentration and substantially equal depth and surface impurity concentration in the surfaces of said first and second semiconductor portions; diffusing the impurity determining the second conductivity type to form seventh, eighth and ninth regions of second conductivity type having substantially equal depth and surface impurity concentration in the surfaces of said first and second regions of first conductivity type and in the surface of said third semiconductor portion; and forming first and second electrodes on the surfaces of said seventh and eighth regions of second conductivity type, a third electrode on the surface of said first region of first conductivity type, a fourth electrode on said fourth region of second conductivity type, a fifth electrode short-circuiting said fifth region of second conductivity type surrounding said second portion and said second region of first conductivity type, and sixth and seventh electrodes respectively on said third semiconductor portion and said sixth region of second conductivity type surrounding it; said first, third and fourth electrodes and respective semiconductor regions connected therewith constituting said transistor portion; said second and fifth electrode and the semiconductor regions connected therewith constituting said first diode portion; and said sixth and seventh electrodes with the corresponding semiconductor regions constituting said second diode portion.

Claim 2

A method for manufacturing a semiconductor integrated circuit means having at least one transistor portion and two diode portions comprising the steps of: preparing a semiconductor substrate of first conductivity type having one principal surface in which first, second and third regions of second conductivity type extend; growing epitaxially a semiconductor layer of first conductivity type having a relatively low impurity concentration to cover said first to third regions of second conductivity type; diffusing the impurity determining the second conductivity type around said first to third regions and forming fourth, fifth and sixth regions of second conductivity type like a closed ring from the surface of said semiconductor layer towards said first to third regions thereunder, thereby surrounding and electrically isolating first, second and third portions of said semiconductor layer of first conductivity type; diffusing the impurity determining the first conductivity type and forming first and second regions of first conductivity type having a relatively high impurity concentration and substantially equal depth and surface impurity concentration in the surfaces of said first and second semiconductor portions; diffusing the impurity determining the second conductivity type to form seventh, eighth and ninth regions of second conductivity type having substantially equal depth and surface impurity concentration in the surfaces of said first and second regions of first conductivity type and in the surface of said third semiconductor portion; and forming first and second electrodes on the surfaces of said seventh and eighth regions of second conductivity type, a third electrode on the surface of said first region of first conductivity type, a fourth electrode on said fourth region of second conductivity type, a fifth electrode short-circuiting said fifth region of second conductivity type surrounding said second portion and said second region of first conductivity type, and sixth and seventh electrodes respectively on said third semiconductor portion and said sixth region of second conductivity type surrounding it; said first, third and fourth electrodes and respective semiconductor regions connected therewith constituting said transistor portion; said second and fifth electrode and the semiconductor regions connected therewith constituting said first diode portion; and said sixth and seventh electrodes with the corresponding semiconductor regions constituting said second diode portion.

Claim 5

A method of manufacturing an integrated circuit device including a transistor having an emitter, base and collector, comprising the steps of: a. forming a first and a second region of a first conductivity type in a major surface of a semiconductor substrate of a second conductivity type; b. forming an epitaxially grown semiconductor layer of the second conductivity type on said major surface of the substrate; c. diffusing an impurity determining the first conductivity type into the epitaxially grown layer to form a third and a fourth region of the first conductivity type reaching said first and second regions respectively, separated from one another and isolating a first and a second portion of said epitaxially grown layer from the remaining portions thereof; d. forming a fifth region of the first conductivity type in said first portion and spacing said fifth region from said first region with a distance shorter than the diffusion length of the minority carriers in said epitaxially grown layer of the second conductivity type by diffusing an impurity determining the first conductivity type in said first portion with a predetermined temperature and time sufficient to form, therein, said fifth region; and e. connecting an emitter, a base and a collector electrode to said fifth region, said first portion and said third region, respectively.

Claim 6

A method of manufacturing an integrated circuit device including a transistor having an emitter, base and collector, comprising the steps of: a. forming a first and a second region of a first conductivity type in a major surface of a semiconductor substrate of a second conductivity type; b. forming an epitaxially grown semiconductor layer of the second conductivity type on said major surface of the substrate; c. diffusing an impurity determining the first conductivity type into the epitaxially grown layer to form a third and a fourth region of the first conductivity type reaching said first and second regions respectively, separated from one another and isolating a first and a second portion of said epitaxially grown layer from the remaining portions thereof; d. forming a fifth region of the first conductivity type in said first portion and spacing said fifth region from said first region with a distance shorter than the diffusion length of the minority carriers in said epitaxially grown layer of the second conductivity type by diffusing an impurity determining the first conductivity type in said first portion with a predetermined temperature and time sufficient to form, therein, said fifth region; and e. connecting an emitter, a base and a collector electrode to said fifth region, said first portion and said third region, respectively.

Claim 7

A method for manufacturing a semiconductor integrated circuit having at least one transistor portion and two diode portions comprising the steps of: preparing a semiconductor substrate of a first conductivity type having one principal surface in which first, second and third regions of a second conductivity type extend; growing epitaxially a semiconductor layer of the first conductivity type having a relatively low impurity concentration to cover said first, second and third regions; diffusing an impurity determining the second conductivity type in a closed shape into said semiconductor layer on said first, second and third regions until reaching said first, second and third regions to form fourth, fifth and sixth regions of the second conductivity type surrounding and electrically isolating first, second and third portions of said semiconductor layer; diffusing an impurity determining the first conductivity type to form seventh and eighth regions of the first conductivity type having a relatively high impurity concentration and substantially equal depth and surface impurity concentration in the surfaces of said first and second semiconductor portions; diffusing an impurity determining the second conductivity type to form ninth, tenth and eleventh regions of the second conductivity type having substantially equal depth and surface impurity concentration in the surfaces of said seventh and eighth regions and in the surface of said third semiconductor portions; and forming first and second electrodes on the surfaces of said ninth and tenth regions, a third electrode on the surface of said seventh region, a fourth electrode on said fourth region, a fifth electrode short-circuiting said fifth region surrounding said second portion and said eighth region, and sixth and seventh electrodes on said third semiconductor portion and said sixth region surrounding said third semiconductor portion, respectively; said first, third and fourth electrodes and respective semiconductor regions connected therewith constituting said transistor portion; said second and fifth electrode and the semiconductor regions conNected therewith constituting said first diode portions; and said sixth and seventh electrodes with the corresponding semiconductor regions constituting said second diode portion.

Claim 8

A method for manufacturing a semiconductor integrated circuit having at least one transistor portion and two diode portions comprising the steps of: preparing a semiconductor substrate of a first conductivity type having one principal surface in which first, second and third regions of a second conductivity type extend; growing epitaxially a semiconductor layer of the first conductivity type having a relatively low impurity concentration to cover said first, second and third regions; diffusing an impurity determining the second conductivity type in a closed shape into said semiconductor layer on said first, second and third regions until reaching said first, second and third regions to form fourth, fifth and sixth regions of the second conductivity type surrounding and electrically isolating first, second and third portions of said semiconductor layer; diffusing an impurity determining the first conductivity type to form seventh and eighth regions of the first conductivity type having a relatively high impurity concentration and substantially equal depth and surface impurity concentration in the surfaces of said first and second semiconductor portions; diffusing an impurity determining the second conductivity type to form ninth, tenth and eleventh regions of the second conductivity type having substantially equal depth and surface impurity concentration in the surfaces of said seventh and eighth regions and in the surface of said third semiconductor portions; and forming first and second electrodes on the surfaces of said ninth and tenth regions, a third electrode on the surface of said seventh region, a fourth electrode on said fourth region, a fifth electrode short-circuiting said fifth region surrounding said second portion and said eighth region, and sixth and seventh electrodes on said third semiconductor portion and said sixth region surrounding said third semiconductor portion, respectively; said first, third and fourth electrodes and respective semiconductor regions connected therewith constituting said transistor portion; said second and fifth electrode and the semiconductor regions conNected therewith constituting said first diode portions; and said sixth and seventh electrodes with the corresponding semiconductor regions constituting said second diode portion.

Claim 10

A method for manufacturing an integrated semiconductor device comprising the steps of: a. selectively diffusing a first conductivity type impurity in a major surface of a semiconductor body of a second conductivity type opposite to the first conductivity type to form a first heavily doped collector region of the first conductivity type; b. epitaxially depositing a semiconductor material of the second conductivity type having a relatively high resistivity on the whole major surface of said body to form an epitaxial semiconductor layer thereon, whereby said first collector region is buried thereunder; c. selectively diffusing an impurity determining the first conductIvity type into said epitaxial semiconductor layer to form a second diffused region of the first conductivity type extending to said first region and surrounding a first portion of said epitaxial layer above said first region, whereby said first portion of said epitaxial layer is electrically isolated from the other portion thereof; d. diffusing an impurity determining the second conductivity type into said first portion of said epitaxial layer to form a base region of the second conductivity type having a relatively low resistivity; e. selectively diffusing an impurity determining the first conductivity type into said diffused base region at a predetermined temperature and for a predetermined time enough to form a heavily doped emitter region of the first conductivity type within said diffused base region and spaced from said collector region with a distance shorter than the diffusion length of the minority carriers in said epitaxial layer; and f. forming an emitter, a base and a collector electrode connected to said emitter region, said base region and said diffused region, respectively.

Claim 11

A method for manufacturing an integrated semiconductor device comprising the steps of: a. selectively diffusing a first conductivity type impurity in a major surface of a semiconductor body of a second conductivity type opposite to the first conductivity type to form a first heavily doped collector region of the first conductivity type; b. epitaxially depositing a semiconductor material of the second conductivity type having a relatively high resistivity on the whole major surface of said body to form an epitaxial semiconductor layer thereon, whereby said first collector region is buried thereunder; c. selectively diffusing an impurity determining the first conductIvity type into said epitaxial semiconductor layer to form a second diffused region of the first conductivity type extending to said first region and surrounding a first portion of said epitaxial layer above said first region, whereby said first portion of said epitaxial layer is electrically isolated from the other portion thereof; d. diffusing an impurity determining the second conductivity type into said first portion of said epitaxial layer to form a base region of the second conductivity type having a relatively low resistivity; e. selectively diffusing an impurity determining the first conductivity type into said diffused base region at a predetermined temperature and for a predetermined time enough to form a heavily doped emitter region of the first conductivity type within said diffused base region and spaced from said collector region with a distance shorter than the diffusion length of the minority carriers in said epitaxial layer; and f. forming an emitter, a base and a collector electrode connected to said emitter region, said base region and said diffused region, respectively.