Full capacity monolithic memory utilizing defective storage cells

Claim 2

For use in a monolithic memory which contains addressing means for addressing memory cells contained in array chips, a plurality of storage array chips arranged on a storage array card; wherein at least one of said chips contains an imperfect memory cell within a known logical chip-sector of said chip; and said one of said chips is located in said memory in a logical card-sector the address of which is related in a predetermined manner to the address of said logical chip-sector; said memory also containing indicating means associated with said addressing means for indicating the location within a memory word of a data bit associated with said imperfect memory cell.

Claim 3

A monolithic memory comprising a plurality of storage array chips arranged on a plurality of storage array cards and adDressing means for addressing words consisting of data stored in a plurality of cells contained in said chips; wherein at least one of said chips contains an imperfect memory cell within a known logical chip-sector of said chip; and said one of said chips is located in said memory in a logical card-sector the address of which is related in a predetermined way to the address of said logical chip-sector; said memory also containing indicating means associated with said addressing means for indicating the location within a memory word of a suspect data bit that is associated with said known chip-sector.

Claim 4

A monolithic memory comprising a plurality of storage array chips arranged on a plurality of storage array cards and adDressing means for addressing words consisting of data stored in a plurality of cells contained in said chips; wherein at least one of said chips contains an imperfect memory cell within a known logical chip-sector of said chip; and said one of said chips is located in said memory in a logical card-sector the address of which is related in a predetermined way to the address of said logical chip-sector; said memory also containing indicating means associated with said addressing means for indicating the location within a memory word of a suspect data bit that is associated with said known chip-sector.

Claim 5

The monolithic memory of claim 2 wherein said indicating means comprises: means for logically combining two portions of an address of a memory word, the result of said logical combination being a representation of the location within said memory word of said suspect data bit.

Claim 6

The monolithic memory of claim 2 further comprising: error detection means for generating an error signal when a data word read from memory contains a given type of error; and error correction means responsive jointly to said indicating means and to said error signal to invert said suspect bit.

Claim 7

The monolithic memory of claim 2 further comprising: additional storage array chips, containing additional storage cells, arranged on one or more storage array cards; and selection means jointly responsive to said address means and to said indicating means for addressing one of said additional storage cells.

Claim 8

The monolithic memory of claim 5 wherein said selection means, during a memory write operation, causes the data bit which would be written into said known chip-sector to be written into said one of said additional storage cells; and said selection means, during a memory read operation, causes a data bit to be read from said one of said additional storage cells.

Claim 9

A monolithic memory comprising a plurality of storage array cards, each of said cards containing m addressable card-sectors, each of said card-sectors containing one or more storage array chips, each of said chips containing m addressable chip-sectors, each of said chip-sectors containing a plurality of memory cells; and word-addressing means for addressing words stored within said memory, each word comprising n bits of data stored in n memory cells, said word-addressing means causing, for each word addressed by the system, substantially simultaneous access to all of the n memory cells associated with a given word-address, each word address containing within it a card-sector-address and a chip-sector-address; wherein at least one of said chips contains at least one imperfect memory cell in its ith chip-sector, each bit of data stored in said ith chip-sector being regarded as a suspect bit; said one of said chips is located in a predetermined card-sector of one of said cards, the address of said card-sector being related in a predetermined manner to the address of said ith chip-sector; said word-addressing means is so arranged that, for each word addressed in said memory, no more than one data bit within a predefined group of data bits within said word will be a suspect bit; said memory also including indicating means responsive to the address of a word to generate a signal representative of the location within said predefined group of said suspect bit.

Claim 10

A monolithic memory comprising a plurality of storage array cards, each of said cards containing m addressable card-sectors, each of said card-sectors containing one or more storage array chips, each of said chips containing m addressable chip-sectors, each of said chip-sectors containing a plurality of memory cells; and word-addressing means for addressing words stored within said memory, each word comprising n bits of data stored in n memory cells, said word-addressing means causing, for each word addressed by the system, substantially simultaneous access to all of the n memory cells associated with a given word-address, each word address containing within it a card-sector-address and a chip-sector-address; wherein at least one of said chips contains at least one imperfect memory cell in its ith chip-sector, each bit of data stored in said ith chip-sector being regarded as a suspect bit; said one of said chips is located in a predetermined card-sector of one of said cards, the address of said card-sector being related in a predetermined manner to the address of said ith chip-sector; said word-addressing means is so arranged that, for each word addressed in said memory, no more than one data bit within a predefined group of data bits within said word will be a suspect bit; said memory also including indicating means responsive to the address of a word to generate a signal representative of the location within said predefined group of said suspect bit.

Claim 11

A monolithic memory comprising a plurality of storage array cards, each of said cards containing m addressable card-sectors, each of said card-sectors containing one or more storage array chips, each of said chips containing m addressable chip-sectors, each of said chip-sectors containing a plurality of memory cells; and word-addressing means for addressing words stored within said memory, each word comprising n bits of data stored in n memory cells, said word-addressing means causing, for each word addressed by the system, substantially simultaneous access to all of the n memory cells associated with a given word-address, each word address containing within it a card-sector-address and a chip-sector-address; wherein: a plurality of said chips each contains at least one imperfect memory cell in one imperfect chip-sector, all of its remaining chip sectors being perfect, each bit of data stored in one of said imperfect chip-sectors being regarded as a suspect bit, and each memory cell within an imperfect chip-sector being regarded as a suspect cell; all chips that are located in the ith card-sector of any of said cards have no known imperfect memory cells in chip-sectors other than the ith chip-sector; said word-addressing means is so arranged that, for each word addressed in said memory, no more than one memory cell within a predefined group of memory cells within the n memory cells associated with the addressed word will be a suspect cell; said memory also includes indicating means responsive to the address of a word to generate a signal representative of the location of a suspect bit within said word.

Claim 12

A monolithic memory comprising a plurality of storage array cards, each of said cards containing m addressable card-sectors, each of said card-sectors containing one or more storage array chips, each of said chips containing m addressable chip-sectors, each of said chip-sectors containing a plurality of memory cells; and word-addressing means for addressing words stored within said memory, each word comprising n bits of data stored in n memory cells, said word-addressing means causing, for each word addressed by the system, substantially simultaneous access to all of the n memory cells associated with a given word-address, each word address containing within it a card-sector-address and a chip-sector-address; wherein: a plurality of said chips each contains at least one imperfect memory cell in one imperfect chip-sector, all of its remaining chip sectors being perfect, each bit of data stored in one of said imperfect chip-sectors being regarded as a suspect bit, and each memory cell within an imperfect chip-sector being regarded as a suspect cell; all chips that are located in the ith card-sector of any of said cards have no known imperfect memory cells in chip-sectors other than the ith chip-sector; said word-addressing means is so arranged that, for each word addressed in said memory, no more than one memory cell within a predefined group of memory cells within the n memory cells associated with the addressed word will be a suspect cell; said memory also includes indicating means responsive to the address of a word to generate a signal representative of the location of a suspect bit within said word.

Claim 13

The monolithic memory of claim 8 wherein said indicating means comprises: means for logically combining two portions of an address of a memory word, the result of said logical combination indicating which of the bits within said word is the suspect bit.

Claim 14

The monolithic memory of claim 8 wherein said word-addressing means comprises: means, associated with each array card that contains a memory cell that is within said predefined group, for providing skewed chip-sector-addresses in such a manner that no two memory cells within said predefined group will have the same chip-sector-address.

Claim 15

The monolithic memory of claim 8 wherein said word-addressing means comprises means, associated with each array card that contains a memory cell that is within said predefined group, for providing skewed addresses for one of said sectors in such a manner that no two memory cells within said predefined group will have both the same chip-sector-address and the same card-sector-address.

Claim 16

The monolithic memory of claim 11 wherein said indicating means comprises: means for logically combining the chip-sector-address portion and the card-sector-address portion of a word-address, the result of said logical combination indicating which of the bits within said word is a suspect bit.

Claim 17

The monolithic memory of claim 8 further comprising: error detection means for generating an error signal when a data word read from memory contains a given type of error; and error correction means responsive jointly to said indicating means and to said error signal to invert the bit that was read from a suspect cell within said predefined group.

Claim 18

The monolithic memory of claim 8 further comprising: an additional storage array card comprising additional storage cells; and selection means jointly responsive to said word-addressing means and to said indicating means for addressing one of said additional storage cells.

Claim 19

The monolithic memory of claim 14 wherein said selection means, during a memory write operation, causes the data bit that is being written into a suspect cell of said predefined group to be written into said one of said additional storage cells; and said selection means, during a memory read operation, causes a bit stored in said one of said additional storage cells to be read out in place of a bit stored in a suspect cell of said predefined group.

Claim 20

A monolithic memory comprising a plurality of storage array units and addressing means for addressing words consisting of data stored in a plurality of cells contained in said units; wherein at least one of said units contains an imperfect memory cell within a known logical unit-sector of said unit; and said one of said units is located in a logical portion of said memory in such a manner that the addRess of said logical portion is related in a predetermined way to the address of said logical unit-sector; said memory also containing indicating means associated with said addressing means for indicatng the location within a memory word of a suspect data bit that is associated with said known unit-sector.

Claim 21

A monolithic memory comprising a plurality of storage array units and addressing means for addressing words consisting of data stored in a plurality of cells contained in said units; wherein at least one of said units contains an imperfect memory cell within a known logical unit-sector of said unit; and said one of said units is located in a logical portion of said memory in such a manner that the addRess of said logical portion is related in a predetermined way to the address of said logical unit-sector; said memory also containing indicating means associated with said addressing means for indicatng the location within a memory word of a suspect data bit that is associated with said known unit-sector.

Claim 22

The monolithic memory of claim 16 wherein said addressing means comprises: means, associated with each array unit that contains a cell within a predefined group, for providing skewed unit-sector-addresses in such a manner that no more than one cell within said predefined group will have the same unit-sector-address.