Specialized array logic

Claim 2

A read only memory comprising: a. a semiconductor body, b. a plurality of cells formed in the semiconductor body, the plurality of cells being located in a matrix of rows and columns, c. a plurality of spaced X lines adapted for support by the body and adapted to receive input digital signals, d. a plurality of Y lines adapted for support by the semiconductor body, e. the plurality of cells each comprising first and second semiconductor regions formed in the body, f. each X line being connected to a plurality of the first regions defining a row, g. selected second regions defining a column being connected to a first one of the Y lines, h. a second Y line immediately adjacent the first Y line being connected to selected second regions in the same column.

Claim 3

A read only memory as in claim 1 wherein: a. the plurality of cells comprise transistors including a collector region, a base region constituting the first region, and an emitter region constituting the second region, b. the adjacent first and second Y lines comprising a conductive metalized line pair, and c. selected emitter regions defining the column being connected to the first Y line, and selected emitter regions defining the same column being connected to the second Y line.

Claim 4

A read only memory as in claim 2 wherein: a. the X lines comprise diffused regions located in the semiconductor body and connected to a plurality of base regions, b. a voltage source means connected to the collector regions, and c. the plurality of cells being responsive to the input digital signals for generating separate distinct signals on the adjacent Y line pair, the distinct signals being indicative of different logic functions.

Claim 5

A read only memory array adaptable for fabrication in monolithic form comprising: a. a first group comprising a plurality of lines extending in a first direction, b. a sEcond group comprising a plurality of lines extending in a second direction, c. the first and second groups being located to define a plurality of coordinate locations, d. the plurality of lines in the second group being adapted to receive digital input signals, e. a first line in the first group having a first output terminal means, f. a second line in the first group being spaced from and adjacent to the first line and having a second output terminal, g. a plurality of semiconductor device means located between the first and second adjacent lines at different coordinate locations and defining a row or column, h. each semiconductor device being connected to different ones of the plurality of lines in the second group, and predetermined semiconductor device means also being selectively connected to either the first or to the second adjacent lines in the first group, and i. the plurality of semiconductor devices being operatively responsive to the digital input signals for simultaneously generating a first output signal on the first output terminal representative of a first logical function and a second output signal on the second output terminal representative of a second logical function.

Claim 6

A read only memory array adaptable for fabrication in monolithic form comprising: a. a first group comprising a plurality of lines extending in a first direction, b. a sEcond group comprising a plurality of lines extending in a second direction, c. the first and second groups being located to define a plurality of coordinate locations, d. the plurality of lines in the second group being adapted to receive digital input signals, e. a first line in the first group having a first output terminal means, f. a second line in the first group being spaced from and adjacent to the first line and having a second output terminal, g. a plurality of semiconductor device means located between the first and second adjacent lines at different coordinate locations and defining a row or column, h. each semiconductor device being connected to different ones of the plurality of lines in the second group, and predetermined semiconductor device means also being selectively connected to either the first or to the second adjacent lines in the first group, and i. the plurality of semiconductor devices being operatively responsive to the digital input signals for simultaneously generating a first output signal on the first output terminal representative of a first logical function and a second output signal on the second output terminal representative of a second logical function.

Claim 7

A read only memory array adaptable for fabrication in monolithic form as in claim 4 further including: a. a semiconductor body, b. the plurality of semiconductor devices comprising a plurality of integrated circuit transistors located in the semiconductor body, each transistor including a first control terminal connected to its associated line in the second group, and each transistor including a second control terminal, predetermined second control terminals being selectively connected to either the first or the second adjacent line in the first group so as to store more than 1 bit of information for a single coordinate location.

Claim 8

A read only memory array adaptable for fabrication in monolithic form as in claim 5 wherein: a. the first adjacent line comprises a metalized line located over the transistors, b. the second adjacent line comprises a metalized line located over the transistors, c. the plurality of transistors defining a row or column each comprising base, emitter, and collector regions, d. each base region being connected to its associated metalized line in the second group, and e. predetermined emitter regions being selectively connected either to the first or the second adjacent metalized line in accordance with the first or second logical function.

Claim 9

A read only memory array adaptable for fabrication in monolithic form as in claim 5 wherein: a. the array includes a plurality of rows and columns of integrated circuit transistors for substantially storing the logical states for 2 bits of information in a single coordinate location.

Claim 10

A read only memory array adaptable for fabrication in monolithic form comprising: a. a substrate, b. a plurality of integrated circuit semiconductor devices located in the substrate so as to define a plurality of rows and columns of semiconductor devices, each semiconductor device having at least first and second control terminals, c. a first group of spaced conductive lines adapted to receive a digital input signal, d. means for connecting each first terminal of a semiconductor device to an associated line in the first group, e. a second group comprising a plurality of spaced conductive lines located in substantially orthogonal relationship to the first group of lines, f. the semiconductor devices defining rows and columns comprising a plurality of semiconductor regions of different conductivity type, the plurality of regions being located between pairs of adjacent first and second lines in the second group, g. the second terminal of predetermined semiconductor devices in a single row or column being selectively connected to either the first or to the second line of its associated pair, and h. the Semiconductor devices in the same single column or row being responsive to the digital input signal for simultaneously generating a first signal representative of a first function on the first line of an associated pair and a second signal representative of a second function on the second line of the same associated pair such that a single device is capable of substantially storing the logical states for 2 bits of information.

Claim 11

A read only memory array adaptable for fabrication in monolithic form comprising: a. a substrate, b. a plurality of integrated circuit semiconductor devices located in the substrate so as to define a plurality of rows and columns of semiconductor devices, each semiconductor device having at least first and second control terminals, c. a first group of spaced conductive lines adapted to receive a digital input signal, d. means for connecting each first terminal of a semiconductor device to an associated line in the first group, e. a second group comprising a plurality of spaced conductive lines located in substantially orthogonal relationship to the first group of lines, f. the semiconductor devices defining rows and columns comprising a plurality of semiconductor regions of different conductivity type, the plurality of regions being located between pairs of adjacent first and second lines in the second group, g. the second terminal of predetermined semiconductor devices in a single row or column being selectively connected to either the first or to the second line of its associated pair, and h. the Semiconductor devices in the same single column or row being responsive to the digital input signal for simultaneously generating a first signal representative of a first function on the first line of an associated pair and a second signal representative of a second function on the second line of the same associated pair such that a single device is capable of substantially storing the logical states for 2 bits of information.

Claim 12

A read only memory array adaptable for fabrication in monolithic form as in claim 8 wherein: a. the plurality of regions for each semiconductor device are constituted by base, emitter, and collector regions, b. the first and second lines of a pair in the second group comprise metallized lines, c. means for connecting each base region of each semiconductor device to an associated line in the first group, and d. means for connecting selected emitter regions in a row or column to either the first or the second metallized lines of its associated pair.

Claim 13

A read only memory array adaptable for fabrication in monolithic form comprising: a. a body of semiconductor material, b. at least one row or column comprising a plurality of semiconductor devices located in the body of semiconductor material, c. each semiconductor device having at least a first and a second semiconductor region of opposite conductivity type, a first terminal opening associated with each first region and a second terminal opening associated with each second region, d. a first plurality of spaced conductive lines extending in a first direction and adaptable for connection to the semiconductor devices and to an input digital word, e. means for connecting the first region of each semiconductor device to separate ones of the first plurality of lines, f. at least a pair of first and second spaced conductive lines extending in a second direction and adaptable for connection to the semiconductor devices, g. the second regions of the semiconductor devices constituting a row or column being situated between the pair of first and second spaced conductive lines, and means for selectively connecting predetermined second terminals to one or the other of the first and second spaced conductive lines extending in the second direction, and h. the semiconductor devices in the row or column being responsive to the digital word for simultaneously generating a first and second signal on the first and second spaced conductive lines extending in the second direction, respectively, the first and second signals being representative of different logical functions.

Claim 14

A read only memory array adaptable for fabrication in monolithic form comprising: a. a body of semiconductor material, b. at least one row or column comprising a plurality of semiconductor devices located in the body of semiconductor material, c. each semiconductor device having at least a first and a second semiconductor region of opposite conductivity type, a first terminal opening associated with each first region and a second terminal opening associated with each second region, d. a first plurality of spaced conductive lines extending in a first direction and adaptable for connection to the semiconductor devices and to an input digital word, e. means for connecting the first region of each semiconductor device to separate ones of the first plurality of lines, f. at least a pair of first and second spaced conductive lines extending in a second direction and adaptable for connection to the semiconductor devices, g. the second regions of the semiconductor devices constituting a row or column being situated between the pair of first and second spaced conductive lines, and means for selectively connecting predetermined second terminals to one or the other of the first and second spaced conductive lines extending in the second direction, and h. the semiconductor devices in the row or column being responsive to the digital word for simultaneously generating a first and second signal on the first and second spaced conductive lines extending in the second direction, respectively, the first and second signals being representative of different logical functions.