Apparatus and method for testing a multi-terminal logic circuit capable of detecting fixed and intermittant faults

Claim 1

Apparatus for testing a multi-terminal logic circuit, having input and output terminals, to determine faults comprising: data circulating means to provide a predetermined sequence of test state patterns, the data content of said data circulating means being programmed to provide said sequence of test state patterns as a function of the logic design of the circuit being tested to provide fault analysis data, said means (providing) continuously cycling through a plurality of cycles of said predetermined sequence of test state patterns, base comparison means to provide a sequence of sets of compare signals, said sequence of sets of compare signals corresponding to the sequence of sets of output signals from a fault free sample of the circuit under test when said sequence of test state patterns is applied to the input terminals of such a fault free sample, a plurality of compare gates, each of said gates having a first input adapted to be coupled to the output signal from a separate one of the output terminals of the logic circuit under test and having a second input coupled to a separate one of said compare signals, each of said compare gates providing a fault indicator signal when the corresponding output terminal signal and compare signal differ to provide a sequence of sets of fault indicator signals, each of said sets of said fault indicator signals being the set of fault indicator signals provided in response to one of said test state patterns where there are one or more fault indicator signals, indicator means synchronized to said data circulating means and responsive to a predetermined Nth set of said fault indicator signals to provide an indication of the step in a cycle of said sequence of test patterns which produces said Nth set of fault signals, means to cause the indication of said step which produces said Nth set of fault indicator signals to automatically jump to an earlier step indication if an Nth set of fault indicator signals is produced at an earlier step in a succeeding cycle of said sequence of test state patterns, hold means to hold a step indication corresponding to an Nth set of fault indicator signals throughout succeeding sets of fault signals and throughout succeeding cycles of said test state patterns until an earlier step of said pattern in a succeeding cycle produces an Nth set of fault signals, and release means to automatically release said hold in response to an earlier step indication of an Nth set of fault signals.

Claim 6

The method of testing a multi-terminal logic circuit, having input and output terminals, to determine faults comprising the steps of continuously circulating a predetermined sequence of test state patterns through a plurality of cycles, the data content of said sequence of test state patterns being programmed to provide said sequence of test state patterns as a function of the logic design of the circuit being tested to provide fault analysis data, generating a sequence of sets of compare signals, said sequence of sets of compare signals corresponding to the sequence of sets of output signals from a fault free sample of the circuit under test when said sequence of test state patterns is applied to the input terminals of such a fault free sample, comparing the separate output signals from the logic circuit under test with corresponding ones of said compare signals, generating a fault indicator signal when the corresponding output signal and compare signal differ to provide a sequence of sets of fault indicator signals, each of said sets of fault indicator signals being the fault indicator signals generated in response to one of said test state patterns where there are one or more fault indicator signals, providing an indication of the step in a cycle of said sequence of test state patterns which produces an Nth set of said fault indicator signals, holding said step indication corresponding to said Nth set of fault signals throughout succeeding sets of fault signals and succeeding cycles of said test state patterns, releasing the hold on said step indication and causing said indication to jump to an earlier step indication if an Nth set of fault indicator signals is produced at an earlier step in a succeeding cycle of said sequence of test state patterns.

Claim 7

The method of testing a multi-terminal logic circuit, having input and output terminals, to determine faults comprising the steps of continuously circulating a predetermined sequence of test state patterns through a plurality of cycles, the data content of said sequence of test state patterns being programmed to provide said sequence of test state patterns as a function of the logic design of the circuit being tested to provide fault analysis data, generating a sequence of sets of compare signals, said sequence of sets of compare signals corresponding to the sequence of sets of output signals from a fault free sample of the circuit under test when said sequence of test state patterns is applied to the input terminals of such a fault free sample, comparing the separate output signals from the logic circuit under test with corresponding ones of said compare signals, generating a fault indicator signal when the corresponding output signal and compare signal differ to provide a sequence of sets of fault indicator signals, each of said sets of fault indicator signals being the fault indicator signals generated in response to one of said test state patterns where there are one or more fault indicator signals, providing an indication of the step in a cycle of said sequence of test state patterns which produces an Nth set of said fault indicator signals, holding said step indication corresponding to said Nth set of fault signals throughout succeeding sets of fault signals and succeeding cycles of said test state patterns, releasing the hold on said step indication and causing said indication to jump to an earlier step indication if an Nth set of fault indicator signals is produced at an earlier step in a succeeding cycle of said sequence of test state patterns.