Patent US3735218A successfully refreshed from Google Patents.
US3735218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for the comparison of two pulse-series frequencies
Assignee: US Philips Corp
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Filing: 1971-05-14
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Granted: 1973-05-22
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Expires: 1991-05-14
Abstract
Abstract A plurality of interconnected AND-gates and flip-flops provide a first output pulse in response to an input pulse series having a frequency higher than a fixed frequency source and a second output in response to a measuring pulse series having a frequency lower than the fixed frequency source. Inputs to the device include a clock pulse signal and a timing pulse signal, both synchronized with the fixed frequency pulse source.
Inventors
- 👤 H Kunert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:56
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
386 words
A device for producing a difference frequency between pulses of a first pulse series having a fixed frequency and a second pulse series having a frequency independent from the first pulse series, comprising first circuit means for receiving the pulses of the first pulse series, second circuit means for receiving pulses of the second series, third circuit means for receiving timing pulses synchronized with the pulses of the first pulse series, and clock pulse circuit means for receiving clock pulses synchronized with the pulses of the timing pulse signal, a first AND-gate means connected to the first circuit means, the second circuit means and the third circuit means for providing a first output for the device in response to the concurrence of pulses from the second pulse series and timing pulse series and the absence of a pulse from the first pulse series, a bistable storage means having a first stable state in response to a pulse on a first input line and having a second stable state in response to a pulse on a second input line, second gate means connected to the third circuit means and to the second circuit means and having an output connected to the first input line of the bistable storage means for setting said storage means to a first stable state in response to the concurrence of a pulse from the first pulse series and the absence of a pulse from the timing pulse series, the second input of the storage means connected to the third circuit means for setting the storage means to a second stable state in response to the presence of a pulse from the timing pulse series, third gate means connected to the storage means and to the first and third circuit means for providing a first device output pulse in response to the concurrence of a pulse from the timing pulse series, the first state of the storage means and an absence of a pulse from the first pulse series, fourth AND-gate means connected to the storage means and to the first and second circuit means for providing a second device output pulse in response to the concurrence of a pulse from the first pulse series, the absence of a pulse from the second pulse series and the second state of the storage means.
Claim 2
Independent Claim
386 words
A device for producing a difference frequency between pulses of a first pulse series having a fixed frequency and a second pulse series having a frequency independent from the first pulse series, comprising first circuit means for receiving the pulses of the first pulse series, second circuit means for receiving pulses of the second series, third circuit means for receiving timing pulses synchronized with the pulses of the first pulse series, and clock pulse circuit means for receiving clock pulses synchronized with the pulses of the timing pulse signal, a first AND-gate means connected to the first circuit means, the second circuit means and the third circuit means for providing a first output for the device in response to the concurrence of pulses from the second pulse series and timing pulse series and the absence of a pulse from the first pulse series, a bistable storage means having a first stable state in response to a pulse on a first input line and having a second stable state in response to a pulse on a second input line, second gate means connected to the third circuit means and to the second circuit means and having an output connected to the first input line of the bistable storage means for setting said storage means to a first stable state in response to the concurrence of a pulse from the first pulse series and the absence of a pulse from the timing pulse series, the second input of the storage means connected to the third circuit means for setting the storage means to a second stable state in response to the presence of a pulse from the timing pulse series, third gate means connected to the storage means and to the first and third circuit means for providing a first device output pulse in response to the concurrence of a pulse from the timing pulse series, the first state of the storage means and an absence of a pulse from the first pulse series, fourth AND-gate means connected to the storage means and to the first and second circuit means for providing a second device output pulse in response to the concurrence of a pulse from the first pulse series, the absence of a pulse from the second pulse series and the second state of the storage means.
Claim 3
Dependent Claim
52 words
A device as claimed in claim 1, further comprising a fifth AND-gate means connected to the storage means and to the second circuit means for providing a first device output pulse in response to the concurrence of the first state of the storage means and a pulse from the second pulse series.
Claim 4
Dependent Claim
59 words
A device as claimed in claim 2 wherein the storage means comprises a bistable trigger, wherein the First and second input lines of the bistable trigger are preparation inputs and wherein the storage means further comprises a trigger input connected to the clock pulse circuit means the storage means being triggerable only during the occurence of a clock pulse.
Claim 5
Dependent Claim
165 words
A device as claimed in claim 3, further comprising a second storage means having a first and second input line and triggerable to a first stable state in response to an input pulse on the first input line thereof and triggerable to a second stable state in response to a pulse on the second input line thereof, sixth gate means connected to the second circuit means, the first storage means, the first circuit means, and the third circuit means for setting the second storage means to a first stable state in response to the concurrence of pulses from the second pulse series and timing pulse series, the absence of a pulse from the first pulse series and the first state of the first storage means, the second storage means being triggerable to a second stable state in response to the absence of a pulse on the first input line thereof, and means connecting the output of the second storage means to the second input circuit.
Claim 6
Dependent Claim
70 words
A device as claimed in claim 4, wherein the second storage means comprises a bistable trigger, wherein the first and second input lines of the second storage means are preparation inputs and wherein the second storage means further comprises a trigger input connected to the clock pulse circuit, the second storage means triggerable only in response to the concurrence of a pulse on a preparation input and a clock pulse.
Claim 7
Dependent Claim
228 words
A device as claimed in claim 3, wherein the second input circuit means comprises a first auxiliary flip-flop triggerable to a first state in response to the concurrence of a clock pulse and the absence of a pulse from the second series of pulses and triggerable to a second stable state in response to the concurrence of a clock pulse and the presence of a pulse from the second series of pulses, a second auxiliary flip-flop triggerable to a first stable state in response to the concurrence of a clock pulse, a feed-back pulse and the first stable state of the first auxiliary flip-flop, the second auxiliary flip-flop being triggerable to a second stable state in response to the concurrence of a clock pulse and the second stable state of the first auxiliary flip-flop, sixth AND-gate means connected to the first and second auxiliary flip-flops for providing the output of the second circuit means in response to the concurrence of the first stable state of the first auxiliary flip-flop and the second stable state of the second auxiliary flip-flop, and a first NAND-gate means for providing the feed-back pulse in response to the absence of a pulse on the output of the second circuit means, or the zero state of the first flip-flop, or a pulse from the first pulse series, or the absence of a timing pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-21 | 1976-11-20 | 1977-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-21 | 1980-11-20 | 1981-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-21 | 1984-11-20 | 1985-05-22 | $7700.00 | Window Closed / Lapsed |