Patent US3733600A successfully refreshed from Google Patents.
US3733600A
Expired / Lapsed
US
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Analog-to-digital converter circuits
Assignee: International Business Machines Corp
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Filing: 1971-04-06
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Granted: 1973-05-15
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Expires: 1991-04-06
Abstract
Abstract Time delays associated with switching controls of analog-todigital converter circuits permit switching transients to be blocked from reducing conversion accuracy. The time delays allow switching to be performed while normal conversion operations are suspended. Appropriate converter components are maintained with quiescent operating levels between conversion cycles so that drifting of those components during conversion cycles is minimized. At least the final portion of a simulated conversion cycle is used as a precedent to each conversion cycle so that the initiating and completing conversion levels are maintained equivalent. A precision semi-conductor switch effects on-off switching with constant resistance by referencing the switch control signals to the switch input level.
Inventors
- 👤 G Hellwarth
- 👤 J Milton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:34
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
207 words
In an apparatus which coverts analog signals introduced to the input thereof into digital manifestations representative of the said analog input signals by performing a sequence of interrelated switching operations between one or more said analog input signals and one or more reference signals, an improvement comprising means responsive to an initiating input for producing an output signal after a predetermined interval of time following said initiating input signal, means operable whenever each switching operation of said predetermined sequence is to be performed by said apparatus for generating the initiating input signal for said predetermined interval signal producing means, means for biasing the said apparatus input at a zero level from the time said initiating input signAl is produced until said predetermined interval of time has passed, and switch controlling means operable in response to said initiating input signal for initiating appropriate said switching operations of said sequence while otherwise preventing any alteration of the state of the circuitry of said apparatus involved in producing the digital manifestation corresponding to the analog input until said predetermined interval signal occurs, whereby the normal analog to digital conversion of said apparatus can be performed without significant adverse effects from transient signals associated with the said sequence of switching operations.
Claim 2
Dependent Claim
207 words
In an apparatus which coverts analog signals introduced to the input thereof into digital manifestations representative of the said analog input signals by performing a sequence of interrelated switching operations between one or more said analog input signals and one or more reference signals, an improvement comprising means responsive to an initiating input for producing an output signal after a predetermined interval of time following said initiating input signal, means operable whenever each switching operation of said predetermined sequence is to be performed by said apparatus for generating the initiating input signal for said predetermined interval signal producing means, means for biasing the said apparatus input at a zero level from the time said initiating input signAl is produced until said predetermined interval of time has passed, and switch controlling means operable in response to said initiating input signal for initiating appropriate said switching operations of said sequence while otherwise preventing any alteration of the state of the circuitry of said apparatus involved in producing the digital manifestation corresponding to the analog input until said predetermined interval signal occurs, whereby the normal analog to digital conversion of said apparatus can be performed without significant adverse effects from transient signals associated with the said sequence of switching operations.
Claim 3
Dependent Claim
65 words
An improved apparatus in accordance with claim 1 which further includes a source of auxiliary reference signal levels having a low impedance at frequencies involved in operation of said apparatus, said auxiliary reference signal levels having magnitudes correlated to the magnitudes of said reference signals, and means for clamping said reference signals to said auxiliary reference signal levels during operation of said switch controlling means.
Claim 4
Dependent Claim
72 words
An improved apparatus in accordance with claim 1 which further includes means for generating a command designating that a conversion cycle is to be performed by said apparatus, means responsive to said command for causing said apparatus to perform at least the final portion of a simulated conversion operation, and means responsive to completion of said simulated conversion for causing said apparatus to perform a complete conversion cycle for an analog input.
Claim 5
Dependent Claim
114 words
An apparatus in accordance with claim 1 wherein said apparatus is a multi-ramp type converter including an integrator circuit and a common node into which said analog and reference signals are switched, the improvement further including a buffer amplifier coupled to receive the signals on said common node, switching means for coupling a signal into said integrator circuit for holding the output thereof fixed during operation of said switch controlling means but for otherwise coupling the output of said buffer amplifier into said integrator circuit, and said predetermined interval signal producing means being arranged for producing a said interval signal output after a sufficient length of time to permit the settling of switching transients.
Claim 6
Dependent Claim
71 words
Apparatus in accordance with claim 4 wherein said switching means includes a switching element for coupling the output of said buffer amplifier into said integrator circuit, and means for controlling the conduction signals for said switching element in correlation to the magnitude of the output of said buffer amplifier for causing said switching element to present a relatively constant resistance for the said amplifier signals being coupled to said integrator circuit.
References Cited (Backward Citations)
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US3577140A
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US3582947A
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US3541320A
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US3566265A
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US3566397A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-14 | 1976-11-13 | 1977-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-14 | 1980-11-13 | 1981-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-14 | 1984-11-13 | 1985-05-15 | $7700.00 | Window Closed / Lapsed |