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Patent US3731004A successfully refreshed from Google Patents.
US3731004A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Impedance matching circuit for tone ringing
Assignee: Microsystems International Ltd
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Filing: 1971-06-01
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Granted: 1973-05-01
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Expires: 1991-06-01
Abstract
Abstract The invention relates to an impedance matching circuit designed to minimize current drain on the supply thereto while maintaining maximum current driving efficiency through a load and particularly adapted to drive an inductive load. The invention has particular applicability to the field of telephony, in that the circuit may be used to drive a tone ringer for a telephone set.
Inventors
- 👤 M Cowpland
- 👤 D Draper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:15
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/022; H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/661; H03K17/662; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/282; H03K3/2823; H04; H04M; H04M19/00; H04M19/02; H04M19/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
210 words
An impedance matching circuit comprising first and second input terminals adapted for connection across an alternating current supply, first and third switching means connected to said first terminal, second and fourth switching means connected to said second terminal, said first and second switching means being series interconnected and said third and fourth switching means being series interconnected, inductive load means connected between the interconnections of said first and second and said third and fourth switching means respectively, first unidirectional current passing means connected across said second switching means, second unidirectional current passing means connected across said fourth switching means, the direction of current flow through each of said unidirectional current passing means being from said second terminal to said first and third switching means respectively, means for connecting said second and fourth switching means to means adapted to alternately close each of said second and fourth sWitching means in a 50 percent duty cycle by application to the control elements thereof of a first switching signal, and means for connecting said first and third switching means to means adapted to close said first and third switching means simultaneously with but for shorter duration than said fourth and second switching means respectively by application to the control elements thereof of pulses.
Claim 2
Dependent Claim
210 words
An impedance matching circuit comprising first and second input terminals adapted for connection across an alternating current supply, first and third switching means connected to said first terminal, second and fourth switching means connected to said second terminal, said first and second switching means being series interconnected and said third and fourth switching means being series interconnected, inductive load means connected between the interconnections of said first and second and said third and fourth switching means respectively, first unidirectional current passing means connected across said second switching means, second unidirectional current passing means connected across said fourth switching means, the direction of current flow through each of said unidirectional current passing means being from said second terminal to said first and third switching means respectively, means for connecting said second and fourth switching means to means adapted to alternately close each of said second and fourth sWitching means in a 50 percent duty cycle by application to the control elements thereof of a first switching signal, and means for connecting said first and third switching means to means adapted to close said first and third switching means simultaneously with but for shorter duration than said fourth and second switching means respectively by application to the control elements thereof of pulses.
Claim 3
Dependent Claim
207 words
An impedance matching circuit comprising first and second input terminals adapted for connection across an alternating current supply, first and third transistors having their collectors connected to said first terminal, second and fourth transistors having their emitters connected to said second terminal, the emitter of said first transistor being connected to the collector of said second transistor and the emitter of said third transistor being connected to the collector of said fourth transistor, inductive load means connected between the emitters of said first and third transistors, first diode means connected across the emitter and collector of said second transistor, second diode means connected across the emitter and collector of said fourth transistor, the anode of each of said first and second diode means being connected to the emitter of each of said second and fourth transistors, means for connecting said second and fourth transistors to means adapted to alternately trigger each of said transistors into conduction by application to the bases thereof of a first switching signal, and means for connecting said first and third transistors to means adapted to trigger said first and third transistors simultaneously with but for shorter duration than said fourth and second transistors respectively by application to the bases thereof of pulses.
Claim 4
Dependent Claim
207 words
An impedance matching circuit comprising first and second input terminals adapted for connection across an alternating current supply, first and third transistors having their collectors connected to said first terminal, second and fourth transistors having their emitters connected to said second terminal, the emitter of said first transistor being connected to the collector of said second transistor and the emitter of said third transistor being connected to the collector of said fourth transistor, inductive load means connected between the emitters of said first and third transistors, first diode means connected across the emitter and collector of said second transistor, second diode means connected across the emitter and collector of said fourth transistor, the anode of each of said first and second diode means being connected to the emitter of each of said second and fourth transistors, means for connecting said second and fourth transistors to means adapted to alternately trigger each of said transistors into conduction by application to the bases thereof of a first switching signal, and means for connecting said first and third transistors to means adapted to trigger said first and third transistors simultaneously with but for shorter duration than said fourth and second transistors respectively by application to the bases thereof of pulses.
Claim 5
Dependent Claim
60 words
The impedance matching circuit of claim 2 wherein said means adapted to trigger said second and fourth transistors comprises a free-running multivibrator providing a square-wave signal and said means to trigger said first and third transistors comprises a capacitive timing circuit adapted to pulse said first and third transistors in synchronization with the leading edges of said square wave signal.
References Cited (Backward Citations)
US3408551A
Cited
US3576443A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-30 | 1976-10-30 | 1977-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-30 | 1980-10-30 | 1981-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-30 | 1984-10-30 | 1985-05-01 | $7700.00 | Window Closed / Lapsed |