Binary two{40 s complement multiplier processing two multiplier bits per cycle

Claim 2

In a binary computer, apparatus for performing multiplication comprising: A. an adder for generating the algebraic binary sum of first and second input operands; B. accumulator means connected to said adder for storing said adder output and for providing said first adder input operand; C. multiplicand means including switching means for selecting multiples of the multiplicand connected to said adder for providing said second adder input operand; D. multiplier means for storing an m bit multiplier factor; E. logic means connected to said multiplier means And said multiplicand switching means and responsive to the state of a plurality n+1 of consecutive multiplier bit positions for selecting an algebraic multiple factor of said multiplicand for application to said adder, the multiple factor having the algebraic value of the examined bits modified as follows, the factor sign is negative if the most significant bit is a one and the factor magnitude is increased by one if the least significant bit is a one and the binary point is considered to follow the first examined bit; F. cycle control means for effecting store of said adder output into said accumulator means and shifting the contents of said multiplier means and said accumulator means by n bit positions; G. termination means for terminating said cycle control means after m/n cycles.

Claim 3

The apparatus of claim 1 further comprising: H. means to initialize said multiplier means with a zero concatenated to the least significant bit.

Claim 4

select a 0 magnitude multiplicand multiple if all examined bits are the same,

Claim 5

select a 0 magnitude multiplicand multiple if all examined bits are the same,

Claim 6

Multiplication apparatus comprising: A. an adder for generating partial products in the form of the binary sum of two operands and including a carry-in input; B. a partial product accumulator register connected to said adder, for storing the accumulated partial products and for providing the first operand input; C. multiplicand register means for storing a multiplicand and selectively applying a multiple, 1/2 , 1 or 0, thereof as the second operand for said adder; D. a multiplier register for storing an m bit multiplier and having an additional position; E. initialization means for loading a multiplier into said multiplier register, effectively multiplied by two and right justified; F. logic means connected to said multiplicand register means and responsive to the two least significant bit positions of said multiplier register and the adjacent bit position for providing a multiplier cycle in accordance with the following rules,

Claim 7

Multiplication apparatus comprising: A. an adder for generating partial products in the form of the binary sum of two operands and including a carry-in input; B. a partial product accumulator register connected to said adder, for storing the accumulated partial products and for providing the first operand input; C. multiplicand register means for storing a multiplicand and selectively applying a multiple, 1/2 , 1 or 0, thereof as the second operand for said adder; D. a multiplier register for storing an m bit multiplier and having an additional position; E. initialization means for loading a multiplier into said multiplier register, effectively multiplied by two and right justified; F. logic means connected to said multiplicand register means and responsive to the two least significant bit positions of said multiplier register and the adjacent bit position for providing a multiplier cycle in accordance with the following rules,

Claim 8

select a 1 magnitude multiplicand multiple if the pair of multiplier bits are the same and differ from the adjacent bit position,

Claim 9

select a 1 magnitude multiplicand multiple if the pair of multiplier bits are the same and differ from the adjacent bit position,

Claim 10

In a binary computer, multiplication apparatus comprising: A. an adder for producing the binary sum of first and second operands; B. an accumulator register connected to said adder for storing said adder output and providing said first input operand; C. a general register for storing a binary multiplicand number; D. a multiplicand factor register for storing a multiple of said multiplicand number and providing said second operand; E. multiplicand switching means connecting said general register to said multiplicand factor register for selectively applying either said multiplicand number or the 1''s complement thereof and selectively applying a multiple of zero, half or one times said multiplicand number; F. a multiplier register for storing a binary number having m bits; G. operand switching means for loading said multiplier register with a number having a zero concatenated as the least significant bit; H. multiplier shifting means for interconnecting the bit positions for causing the contents of said multiplier register to be shifted right two bit positions; I. partial product shifting means interconnecting Said adder and said accumulator register for arithmetically shifting said adder output two bit positions right; J. counting means for controlling the number of multiplication cycles, including means for initializing for a count m/2; K. multiplicand factor selection means connected to said multiplicand switching means and responsive to the three least significant bits of said multiplier register for selecting the true form of said multiplicand number or its 1''s complement and an adder carry-in in accordance with the most significant of the three bits and for selecting a multiple of said multiplicand in accordance with the two least significant bits, the least significant bit being rounded up if ''''1,'''' and the result being construed in accordance with the following table: Multiplier Bits Multiplicand Factor 0 00 0 0 01 1/2 0 10 1/2 0 11 1 1 00 -1 1 01 - 1/2 1 10 - 1/2 1 11 0 L. cycle control means responsive to said counting means for cyclically gating said accumulator and multiplicand registers, shifting said multiplier register contents, and decrementing said counting means until a count of zero is reached.

Claim 11

In a binary computer, multiplication apparatus comprising: A. an adder for producing the binary sum of first and second operands; B. an accumulator register connected to said adder for storing said adder output and providing said first input operand; C. a general register for storing a binary multiplicand number; D. a multiplicand factor register for storing a multiple of said multiplicand number and providing said second operand; E. multiplicand switching means connecting said general register to said multiplicand factor register for selectively applying either said multiplicand number or the 1''s complement thereof and selectively applying a multiple of zero, half or one times said multiplicand number; F. a multiplier register for storing a binary number having m bits; G. operand switching means for loading said multiplier register with a number having a zero concatenated as the least significant bit; H. multiplier shifting means for interconnecting the bit positions for causing the contents of said multiplier register to be shifted right two bit positions; I. partial product shifting means interconnecting Said adder and said accumulator register for arithmetically shifting said adder output two bit positions right; J. counting means for controlling the number of multiplication cycles, including means for initializing for a count m/2; K. multiplicand factor selection means connected to said multiplicand switching means and responsive to the three least significant bits of said multiplier register for selecting the true form of said multiplicand number or its 1''s complement and an adder carry-in in accordance with the most significant of the three bits and for selecting a multiple of said multiplicand in accordance with the two least significant bits, the least significant bit being rounded up if ''''1,'''' and the result being construed in accordance with the following table: Multiplier Bits Multiplicand Factor 0 00 0 0 01 1/2 0 10 1/2 0 11 1 1 00 -1 1 01 - 1/2 1 10 - 1/2 1 11 0 L. cycle control means responsive to said counting means for cyclically gating said accumulator and multiplicand registers, shifting said multiplier register contents, and decrementing said counting means until a count of zero is reached.

Claim 12

select a 1/2 magnitude multiplicand multiple if the pair of multiplier bits differ; G. cycle control means for producing exactly m/2 multiplier cycles, and for each cycle, storing said adder output in said partial product accumulator register having the register''s contents shifted right by 2 bit positions except for the last cycle, effecting the add operation, and shifting said multiplier register 2 bit positions to the right.

Claim 13

select a 1/2 magnitude multiplicand multiple if the pair of multiplier bits differ; G. cycle control means for producing exactly m/2 multiplier cycles, and for each cycle, storing said adder output in said partial product accumulator register having the register''s contents shifted right by 2 bit positions except for the last cycle, effecting the add operation, and shifting said multiplier register 2 bit positions to the right.