Converting circuit for a line-sequential television signal recording device

Claim 2

A circuit for converting a simultaneous television signal of a selected line frequency comprising means for reducing the vertical definition of at least a component of said simultaneous signal thereby to produce a modified signal; and a first switch means coupled to said reducing means to receive said modified signal for converting said modified signal into a sequential signal, said switch operating at and synchronized with said line frequency, whereby said modified sequeNtial signal is adapted to be recorded and reconverted upon playback into a simultaneous signal without interference effects.

Claim 3

A circuit as claimed in claim 1 wherein said switch means comprises two input means for receiving different components of said simultaneous signal respectively, at least one of said inputs being coupled to said reducing means, and an output means for supplying said sequential signal.

Claim 4

A circuit as claimed in claim 2 wherein said reducing means comprises an electronic spot wobbler circuit.

Claim 5

A circuit as claimed in claim 3 wherein said wobbler comprises a modulator having an input coupled to receive said simultaneous signal source and an output, a delay line having a time delay equal to one horizontal line coupled to said modulator output, a first diode coupled to said delay line, a second diode poled opposite to said diode coupled to said modulator output, means for combining the outputs of said diodes, and a demodulator.

Claim 6

A circuit as claimed in claim 2 wherein said reducing means comprises a delay line having a time delay of one horizontal line and having an input coupled to receive said simultaneous signal and an output; and an adder having inputs coupled to receive said simultaneous signal and said delay line output respectively, and an output coupled to said switch.

Claim 7

A circuit as claimed in claim 2 wherein said reducing means comprises a second switch operated in synchronism with said first switch and having first and second input means, one of said inputs being coupled to receive said simultaneous signal and an output; a delay line having an input coupled to said second switch output and an output; an adder having inputs coupled to said delay line output and to receive said simultaneous signal respectively, and an output coupled to the remaining second switch input.

Claim 8

A circuit as claimed in claim 6 further comprising a pair of filters having inputs coupled to said adder and delay line outputs respectively, and outputs coupled to said first switch inputs respectively.

Claim 9

A circuit as claimed in claim 2 wherein said reducing means comprises a second switch synchronized with said first switch and having two inputs and an output, one of said inputs being coupled to receive said simultaneous signal; a delay line having an input coupled to said second switch output and an output coupled to one of said first switch inputs; a subtraction circuit having inputs coupled to said delay line output and to receive said simultaneous signal respectively, and an output coupled to the remaining input of said second switch; an adder circuit having inputs coupled to receive said simultaneous signal and to said delay line output respectively, and an output coupled to the remaining input of said first switch.

Claim 10

A circuit as claimed in claim 2 further comprising a recording medium, recording and reproducing transducers coupled to said medium, said recording transducer being coupled to said first switch output, and a sequential to simultaneous translator coupled to said reproducing transducer.

Claim 11

A circuit as claimed in claim 9 wherein said translator comprises first and second serially coupled in the order recited delay lines, each having an input and an output; a first adder having a first input coupled to said first delay line input and said reproducing transducer, a second input coupled to said second delay line output, and an output; second and third switches each having first and second inputs and an output; said first input of said second switch being coupled to said adder output and said second input of said third switch; said second input of said second switch being coupled to said first input of said third switch and to the junction of said delay lines; a second adder having two inputs coupled to said outputs of said second and third switches respectively, and an output means for providing a reproduced simultaneous signal.

Claim 12

A circuit as claimed in claim 9 wherein said translator comprises first and second delay lines eacH having an input and an output; second and third switches each having two inputs and an output; said second switch output being coupled to said first delay line input; said second switch second input being coupled to said reproducing transducer and said third switch first input, said second delay line output being coupled to said third switch second input; an adder having two inputs and an output means for providing said simultaneous signal; said first adder input being coupled to said first delay line output and said second switch first input; and said second adder input being coupled to said third switch output.

Claim 13

A circuit as claimed in claim 9 wherein said translator comprises second and third switches each having a first input, a second input coupled to said reproducing transducer, and an output; first and second delay lines each having an input coupled to said second and third switch outputs respectively, and an output coupled to said second and third switch first inputs respectively, first and second adders each having a first input coupled to said first and second delay line inputs respectively, a second input coupled to said first and second delay line outputs respectively, and an output; and a third adder having two inputs coupled to said first and second adder outputs respectively, and an output means for providing a reproduced simultaneous signal.

Claim 14

A circuit as claimed in claim 9 wherein said translator comprises second and third switches each having first and second inputs and an output; a delay line having an input coupled to said second switch output, and an output; an adder having first input coupled to said second switch second input and said reproducing transducer, a second input coupled to said delay line output and said third switch second input, and an output coupled to said first inputs of said second and third switches.

Claim 15

A circuit as claimed in claim 9 wherein said translator comprises a second switch having two inputs and an output; a delay line having an input coupled to said second switch output, and an output; an adder having two inputs and two outputs; said first adder input being coupled to said reproducing transducer and said second switch second input; said second adder input being coupled to delay line output; said first adder output being coupled to said second switch first input; and said second adder output providing a reproduced simultaneous signal.