Branch facility diagnostics

Claim 2

An electronic data processing control element having a micro instruction modifying system for generating in an unmodified state a first type micro-op signal for controlling a predetermined micro operation, said first type micro-op signal generated in response to a first type micro instruction signal having a first predetermined pattern of bits, and in a modified state said modifying system generating a second type micro-op signal for controlling said predetermined micro operation, said second type micro-op signal generated in response to any modified first type micro-op signal in response to a micro instruction signal having any pattern of bits other than said first predetermined pattern of bits, said unmodified first type microop signal and said second type micro-op signal for controlling the same operation, said control element comprising: a. a first generating means responsive to said first type micro instruction having said first predetermined pattern of bits for generating said unmodified first type micro-op signal; b. modifying means responsive to any of a predetermined set of branching micro instruction signals for providing at least one modifying signal; c. and second generating means coupled to said first generating means aNd to said modifying means for generating said second type micro-op signal in response to said modifying signal and to said unmodified first type micro-op signal.

Claim 3

A micro instruction modifying system as recited in claim 1 wherein said generating means is responsive to a halt (HLT) micro instruction having said predetermined pattern of bits for generating a half (HLT) micro-op signal.

Claim 4

A micro instruction modifying system as recited in claim 1 wherein said first type micro-op signal is a ''''halt'''' for halting the execution of a micro program then under execution.

Claim 5

A micro instruction modifying system as recited in claim 1 wherein said predetermined set of branching micro instruction signals are selected from the group consisting of ''''MAINTRA2R'''' and ''''STOBRN.''''

Claim 6

A micro instruction modifying system as recited in claim 4 wherein said predetermined set of branching micro instruction signals call for a branch to one of two complementary ROM locations ''''0003'''' or ''''7774'''' (octal).

Claim 7

A micro instruction modifying system as recited in claim 1, wherein said modifying means comprise a flip-flop, AND gates and NAND gates said AND gates exclusive OR coupled together and with predetermined ones of said NAND gates serially coupled to each other, and having predetermined ones of said serially coupled NAND gates coupled to predetermined ones of said AND gates, and the operation of said generating means is modified by setting the flip-flop.

Claim 8

A micro instruction modifying system as recited in claim 1 including sub-command generating means coupled to said signal enabling means for generating sub-commands for controlling branching of the branching micro instruction signals.

Claim 9

A micro instruction modifying system as recited in claim 7 wherein said sub-command generating means generate the sub-command signals FNR, FAR, and FRA for controlling the branching of MAINTRA2R and STOBRN micro instruction signals.

Claim 10

A micro instruction modifying system as recited in claim 8 wherein said modifying system includes a read only memory (ROM), and coupled to said ROM further includes an address register and a local register.

Claim 11

A micro instruction modifying system as recited in claim 9 wherein said signal enabling means provides two enabling signals Alpha and Beta .

Claim 12

A micro instruction modifying system as recited in claim 10 wherein Alpha is true when the following Boolean expression is true; a. Alpha U14.U13.U12.U11.U10.U09.U08.U07.U06.U05.U04.U03.U02.U01, and Beta is true when the following Boolean expression is true; b. Beta U14.U13.U12.U11.U10.U09.U08.U07.U06.U05.U04.U03.U02.U01, and wherein Un represents ROM bit positions of the U-register.

Claim 13

In combination with a ROM system having an address register, a ROM local register, a micro instruction decoder and a working store register a diagnostic system for confidence testing of ROM branching capabilities of a computer system comprising: a. generating means for generating in response to a halt HLT micro instruction signal a halt (HLT) micro-op signal for causing a computer program to halt; b. predetermined storage locations in said ROM for storing at least one of the HLT micro instructions; c. enabling means responsive to a first predetermined set of branch micro instructions, said first predetermined set of micro instructions calling for a branch to predetermined ones of said predetermined ROM storage locations, said modifying means for generating an enabling signal.

Claim 14

In combination with a ROM system having an address register, a ROM local register, a micro instruction decoder and a working store register a diagnostic system for confidence testing of ROM branching capabilities of a computer system comprising: a. generating means for generating in response to a halt HLT micro instruction signal a halt (HLT) micro-op signal for causing a computer program to halt; b. predetermined storage locations in said ROM for storing at least one of the HLT micro instructions; c. enabling means responsive to a first predetermined set of branch micro instructions, said first predetermined set of micro instructions calling for a branch to predetermined ones of said predetermined ROM storage locations, said modifying means for generating an enabling signal.

Claim 15

A diagnostic system for confidence testing as recited in claim 12 wherein said predetermined storage locAtions are ROM storage locations and a HLT micro instruction is stored in said predetermined ROM locations.

Claim 16

A diagnostic system for diagnosis and confidence testing of ROM branching capabilities of a computer system comprising: a. a computer read only memory (ROM) for storing micro instructions; b. a working store register coupled to said ROM; c. a ROM address register coupled to said ROM and to said working store register; d. a ROM local register coupled to said ROM, to said ROM address register and to said micro instruction decoder; e. branch logic means coupled to said ROM local register, ROM address register and working store register, said branch logic means for controlling the branching of a branch micro instruction; f. first means coupled to said ROM local register and responsive to a first predetermined pattern of bits in said ROM local register for generating a HALT micro-op for effecting upon execution the halting of said computer; g. second means coupled to said ROM local register and responsive to a second predetermined pattern of bits in said ROM local register for generating a FAR sub-command signal; h. third means coupled to said ROM local register and responsive to a third predetermined pattern of bits for generating an FNR sub-command signal; i. fourth means coupled to said ROM local register and responsive to a predetermined bit in said ROM local register and to said FNR sub-command for generating a FAR sub-command signal; j. fifth means responsive to a fifth predetermined pattern of bits in said ROM local register for generating a first modifying signal; and k. sixth means responsive to said modifying signal for modifying said HLT micro-op signal, said modification for effecting, upon execution of said HLT micro-op signal, the continued running of said computer wherein said FAR sub-command signal controls the transfer of the contents of the working store register to the address register, and said FNR sub-command signal controls the transfer of the contents of the local register to the address register.

Claim 17

A diagnostic system for diagnosis and confidence testing of ROM branching capabilities of a computer system comprising: a. a computer read only memory (ROM) for storing micro instructions; b. a working store register coupled to said ROM; c. a ROM address register coupled to said ROM and to said working store register; d. a ROM local register coupled to said ROM, to said ROM address register and to said micro instruction decoder; e. branch logic means coupled to said ROM local register, ROM address register and working store register, said branch logic means for controlling the branching of a branch micro instruction; f. first means coupled to said ROM local register and responsive to a first predetermined pattern of bits in said ROM local register for generating a HALT micro-op for effecting upon execution the halting of said computer; g. second means coupled to said ROM local register and responsive to a second predetermined pattern of bits in said ROM local register for generating a FAR sub-command signal; h. third means coupled to said ROM local register and responsive to a third predetermined pattern of bits for generating an FNR sub-command signal; i. fourth means coupled to said ROM local register and responsive to a predetermined bit in said ROM local register and to said FNR sub-command for generating a FAR sub-command signal; j. fifth means responsive to a fifth predetermined pattern of bits in said ROM local register for generating a first modifying signal; and k. sixth means responsive to said modifying signal for modifying said HLT micro-op signal, said modification for effecting, upon execution of said HLT micro-op signal, the continued running of said computer wherein said FAR sub-command signal controls the transfer of the contents of the working store register to the address register, and said FNR sub-command signal controls the transfer of the contents of the local register to the address register.

Claim 18

In combination with the read only memory system (ROM) a method for confidence testing of ROM branching capabilities of a computer system comprising the steps of: a. storing a halt (HLT) micro instruction in first and second predetermined locations of said ROM, said HLT micro instruction for generating a HLT micro-op for halting a computer micro program running on said computer systems; b. modifying the HLT micro-op in response to a store and branch (STOBRN) micro instruction calling for a branch to one of said first predetermined locations, whereupon said modified HLT micro-op permits upon execution, the micro program to continue to run; c. branching to one of said first predetermined locations in response to the STOBRN micro instruction; d. and executing the modified HLT micro-op whereupon the micro program continues to run.

Claim 19

In combination with the read only memory system (ROM) a method for confidence testing of ROM branching capabilities of a computer system comprising the steps of: a. storing a halt (HLT) micro instruction in first and second predetermined locations of said ROM, said HLT micro instruction for generating a HLT micro-op for halting a computer micro program running on said computer systems; b. modifying the HLT micro-op in response to a store and branch (STOBRN) micro instruction calling for a branch to one of said first predetermined locations, whereupon said modified HLT micro-op permits upon execution, the micro program to continue to run; c. branching to one of said first predetermined locations in response to the STOBRN micro instruction; d. and executing the modified HLT micro-op whereupon the micro program continues to run.

Claim 20

A method as recited in claim 15 whereupon the execution of a modified HLT micro-op the micro program continues to run and a next MAINTRA2R micro instruction is fetched and executed, said MAINTRA2R micro instruction modifying the HLT micro-op, and also effecting a branch to another of said first predetermined locations.

Claim 21

In combination with a read only memory system (ROM) having signal modifying means a method for confidence testing of ROM branching capabilities of a computer system comprising the steps of: a. allocating storage locations in a ROM for storing micro instructions therein; b. storing in predetermined ones of said storage locations a halt (HLT) micro instruction, which when executed halts the further execution of a micro program; c. storing in the remaining of said allocated storage locations, branch micro instructions selected from a predetermined set, said branch micro instructions calling for a branch to one of said predetermined locations containing a HLT micro instruction, said branch micro instruction also capable of effecting the modification of the halt (HLT) micro instruction so that upon execution of the HLT micro instruction the further execution of the micro program continues; d. executing the first branch micro instruction stored in a first one of said remaining allocated storage locations, said branch micro instruction calling for a branch to a first one of said predetermined storage locations storing a HLT micro instruction; e. modifying in response to the first branch micro instruction, the HLT micro instructions stored in said first one of said predetermined storage locations storing a HLT micro instruction, so that upon execution of said HLT micro instructions stored in said first one of said predetermined storage locations, the further execution of the micro program continues; f. branching in response to the first branch micro instruction, to said first one of said predetermined storage locations storing a HLT micro instruction; and g. executing said HLT micro instruction stored in said first one of said predetermined storage locations storing a HLT micro instruction, whereupon with the execution of said HLT micro instruction, the micro program continues to run.

Claim 22

In combination with a read only memory system (ROM) having signal modifying means a method for confidence testing of ROM branching capabilities of a computer system comprising the steps of: a. allocating storage locations in a ROM for storing micro instructions therein; b. storing in predetermined ones of said storage locations a halt (HLT) micro instruction, which when executed halts the further execution of a micro program; c. storing in the remaining of said allocated storage locations, branch micro instructions selected from a predetermined set, said branch micro instructions calling for a branch to one of said predetermined locations containing a HLT micro instruction, said branch micro instruction also capable of effecting the modification of the halt (HLT) micro instruction so that upon execution of the HLT micro instruction the further execution of the micro program continues; d. executing the first branch micro instruction stored in a first one of said remaining allocated storage locations, said branch micro instruction calling for a branch to a first one of said predetermined storage locations storing a HLT micro instruction; e. modifying in response to the first branch micro instruction, the HLT micro instructions stored in said first one of said predetermined storage locations storing a HLT micro instruction, so that upon execution of said HLT micro instructions stored in said first one of said predetermined storage locations, the further execution of the micro program continues; f. branching in response to the first branch micro instruction, to said first one of said predetermined storage locations storing a HLT micro instruction; and g. executing said HLT micro instruction stored in said first one of said predetermined storage locations storing a HLT micro instruction, whereupon with the execution of said HLT micro instruction, the micro program continues to run.

Claim 23

A method as recited in claim 17 wherein branching in response to the first branch micro instruction fails to occur and the execution of said HLT micro instruction stored in said first one of said predetermined storage locations does not take place, whereupon an unmodified HLT micro instruction stored in a second one of said predetermined storage locations is executed causing the micro program to halt.

Claim 24

A method as recited in claim 17 wherein a MAINTRA2R micro instruction is stored in said first one of said remaining allocated storage locations.

Claim 25

In combination with a read only memory system (roM) a method for confidence testing of ROM branch capabilities of a computer system comprising the steps of: a. allocating in a ROM, storage locations 0003, 0004, 0005, 0006 and their respective complementary locations 7771, 7772, 7773, and 7774 for storing predetermined micro instructions therein; b. storing predetermined micro instructions in said locations in accordance with the following Table I; Table I ROM Location Micro Instruction Stored 0003 HALT 0004 MAINTRA2R 0005 HALT 0006 STOBRN 7774 7771 STOBRN 0003 7772 HALT 7773 MAINTRA2R 7774 HALT Alpha . wherein MAINTRA2R is a branch micro instruction for branching back to an original micro program and is capable of modifying a HALT micro instruction so that the HALT micro instruction that is modified effects the continued running of the micro program; Beta . and wherein a STOBRN is a branch micro instruction calling for a branch of the micro program to any ROM location and moreover when a branch is called for to location 0003 or 7774 said STOBRN is capable of modifying the HALT micro instruction so that the micro instruction that is modified effects the continued running of the micro program; gamma . and wherein the HALT micro instruction not modified by another micro instruction is capable of effecting the halting of the micro program; c. executing the STOBRN micro instruction stored in ROM location 7771, said execution causing a branch to location 0003 and modifying said HALT instruction stored in location 0003; d. executing said modified HALT instruction stored in ROM location 0003, said execution causing the micro program to continue to the next ROM location 0004 storing a MAINTRA2R micro instruction; e. executing said MAINTRA2R micro instruction stored in location 0004, said execution causing a branch back to location 7772 and also modifying said HALT instruction stored in location 7772; f. executing said modified HALT instructiOn stored in ROM location 7772, said execution causing the micro program to continue to the next ROM location 7773 storing a MAINTRA2R micro instruction; g. executing said MAINTRA2R micro instruction stored in location 7773, said execution causing a branch back to location 0005 and also modifying said HALT micro instruction stored in location 0005; h. executing said modified HALT instruction stored in ROM location 0005, said execution causing the micro program to continue to the next ROM location 0006 storing a store-and-branch to location 7774 (STOBRN 7774) micro instruction; i. executing said STOBRN 7774 micro instruction, said execution causing a branch to location 7774 and also modifying the HALT micro instruction stored in location 7774; j. and executing said modified HALT micro instruction stored in ROM location 7774, said execution causing the micro program to continue to the next ROM location.

Claim 26

In combination with a read only memory system (roM) a method for confidence testing of ROM branch capabilities of a computer system comprising the steps of: a. allocating in a ROM, storage locations 0003, 0004, 0005, 0006 and their respective complementary locations 7771, 7772, 7773, and 7774 for storing predetermined micro instructions therein; b. storing predetermined micro instructions in said locations in accordance with the following Table I; Table I ROM Location Micro Instruction Stored 0003 HALT 0004 MAINTRA2R 0005 HALT 0006 STOBRN 7774 7771 STOBRN 0003 7772 HALT 7773 MAINTRA2R 7774 HALT Alpha . wherein MAINTRA2R is a branch micro instruction for branching back to an original micro program and is capable of modifying a HALT micro instruction so that the HALT micro instruction that is modified effects the continued running of the micro program; Beta . and wherein a STOBRN is a branch micro instruction calling for a branch of the micro program to any ROM location and moreover when a branch is called for to location 0003 or 7774 said STOBRN is capable of modifying the HALT micro instruction so that the micro instruction that is modified effects the continued running of the micro program; gamma . and wherein the HALT micro instruction not modified by another micro instruction is capable of effecting the halting of the micro program; c. executing the STOBRN micro instruction stored in ROM location 7771, said execution causing a branch to location 0003 and modifying said HALT instruction stored in location 0003; d. executing said modified HALT instruction stored in ROM location 0003, said execution causing the micro program to continue to the next ROM location 0004 storing a MAINTRA2R micro instruction; e. executing said MAINTRA2R micro instruction stored in location 0004, said execution causing a branch back to location 7772 and also modifying said HALT instruction stored in location 7772; f. executing said modified HALT instructiOn stored in ROM location 7772, said execution causing the micro program to continue to the next ROM location 7773 storing a MAINTRA2R micro instruction; g. executing said MAINTRA2R micro instruction stored in location 7773, said execution causing a branch back to location 0005 and also modifying said HALT micro instruction stored in location 0005; h. executing said modified HALT instruction stored in ROM location 0005, said execution causing the micro program to continue to the next ROM location 0006 storing a store-and-branch to location 7774 (STOBRN 7774) micro instruction; i. executing said STOBRN 7774 micro instruction, said execution causing a branch to location 7774 and also modifying the HALT micro instruction stored in location 7774; j. and executing said modified HALT micro instruction stored in ROM location 7774, said execution causing the micro program to continue to the next ROM location.

Claim 27

An electronic data processing control element having an instruction modifying system for generating in an unmodified state a first type signal for controlling a predetermined operation, said first type signal generated in response to a first type instruction signal having a first predetermined pattern of bits, and in a modified state said modifying system generating a second type signal for controlling said predetermined operation, said second type signal generated in response to any modified first type signal in response to an instruction signal having any pattern of bits other than said first predetermined pattern of bits, said unmodified first type signal and said second type signal for controlling the same operation, said control element comprising: a. a first generating means responsive to said first type instruction having said first predetermined pattern of bits for generating said unmodified first type signal; b. modifying means responsive to any of a predetermined set of branching instruction signals for providing at least one modifying signal; c. and second generating means coupled to said first generating means and to said modifying means for generating said second type signal in response to said modifying signal and to said unmodified first type signal.

Claim 28

An electronic data processing control element having an instruction modifying system for generating in an unmodified state a first type signal for controlling a predetermined operation, said first type signal generated in response to a first type instruction signal having a first predetermined pattern of bits, and in a modified state said modifying system generating a second type signal for controlling said predetermined operation, said second type signal generated in response to any modified first type signal in response to an instruction signal having any pattern of bits other than said first predetermined pattern of bits, said unmodified first type signal and said second type signal for controlling the same operation, said control element comprising: a. a first generating means responsive to said first type instruction having said first predetermined pattern of bits for generating said unmodified first type signal; b. modifying means responsive to any of a predetermined set of branching instruction signals for providing at least one modifying signal; c. and second generating means coupled to said first generating means and to said modifying means for generating said second type signal in response to said modifying signal and to said unmodified first type signal.