Computer input-output chaining system

Claim 2

In an I/O system including a computer having a main memory, the memory having a dedicated counter location dedicated to an I/O controller for addressing sequential memory locations each of which contains the address of a data address counter for sequentially addressing memory word locations containing a block of data words, an I/O controller comprising, an address register, means to supply the address of the dedicated counter location to the computer and to receive in said address register the address of a first data address counter, means to successively supply the content of said address register to the computer and to successively transfer the data words of a block, means operative in response to a first stimulus to again supply the address of the dedicated counter location to the computer and to receive in said address register the address of a next data address counter for use in transferring data words of a next block, and means operative in response to a second stimulus to subsequently terminate the I/O operation.

Claim 3

A controller as defined in claim 1 wherein said first stimulus is an overflow signal received from the computer during a data word transfer.

Claim 4

A controller as defined in claim 1 wherein said first stimulus is the presence of a first predetermined control character in a transferred data word.

Claim 5

A controller as definEd in claim 1 wherein said second stimulus is an overflow signal received from the computer during use of the dedicated counter location.

Claim 6

A controller as defined in claim 1 wherein said second stimulus is the presence of a second predetermined control character in a transferred data word.

Claim 7

In an I/O system including a computer having a main memory, the memory having a dedicated counter location dedicated to an I/O controller for addressing sequential memory locations each of which contains the address of a data address counter for sequentially addressing memory word locations containing a block of data words, an I/O controller comprising, an address register, an address bus, and a data bus, means using said address bus to supply the address of the dedicated counter location to the computer, and using said data bus to receive in said address register the address of a first data address counter, means using said address bus to successively supply the content of said address register to the computer, and using said data bus to successively transfer data words of a block, means operative in response to an overflow signal received from the computer during a data word transfer to again supply the address of the dedicated counter location over said address bus to the computer, and to use said data bus to receive in said address register the address of a next data address counter for use in transferring data words of a next block, and means operative in response to an overflow signal received from the computer during use of said dedicated counter location to subsequently terminate the I/O operation.

Claim 8

In an I/O system including a computer having a main memory, the memory having a dedicated counter location dedicated to an I/O controller for addressing sequential memory locations each of which contains the address of a data address counter for sequentially addressing memory word locations containing a block of data words, an I/O controller comprising, an address register, an address bus, and a data bus, means using said address bus to supply the address of the dedicated counter location to the computer, and using said data bus to receive in said address register the address of a first data address counter, means using said address bus to successively supply the content of said address register to the computer, and using said data bus to successively transfer data words of a block, means operative in response to an overflow signal received from the computer during a data word transfer to again supply the address of the dedicated counter location over said address bus to the computer, and to use said data bus to receive in said address register the address of a next data address counter for use in transferring data words of a next block, and means operative in response to an overflow signal received from the computer during use of said dedicated counter location to subsequently terminate the I/O operation.

Claim 9

In an I/O system including at least one I/O device and a computer having a main memory, the memory having a dedicated counter location dedicated to an I/O controller for addressing sequential memory locations each of which contains the address of a data address counter for sequentially addressing memory word locations containing a block of data words, an I/O controller, comprising a first flip-flop responsive to a decoded command from the computer to store a memory chaining status, a second flip-flop having an initial ''''wired address'''' state, an address register, an address bus, and a data bus, means conditioned by the ''''wired address'''' state of said second flip-flop to supply over said address bus the address of the dedicated counter location to the computer, and over said data bus to receive in said address register the address of a first data address counter, and to change said second flip-flop to an ''''address register'''' state, means conditioned by the ''''address register'''' state of said second flip-flop and using said address bus to successively supply the content of said address register to the computer and using said data bus to successively transfer data words of a block, a third flip-flop conditioned by the ''''address register'''' state of said second flip-flop and an overflow signal received from the computer to assume a ''''word overflow'''' state, means to change the second flip-flop to its ''''wired address'''' state for the supplying of the address of the dedicated counter location to the computer, and to return the second flip-flop to its ''''address register'''' state for the transferring of data words of a next block, a fourth flip-flop conditioned by a ''''wired address'''' state of said second flip-flop and an overflow signal received from the computer to assume a ''''block overflow'''' state, and means responsive to the ''''word overflow'''' and ''''block overflow'''' states of said third and fourth flip-flops to cause a termination of the I/O operation.

Claim 10

In an I/O system including at least one I/O device and a computer having a main memory, the memory having a dedicated counter location dedicated to an I/O controller for addressing sequential memory locations each of which contains the address of a data address counter for sequentially addressing memory word locations containing a block of data words, an I/O controller, comprising a first flip-flop responsive to a decoded command from the computer to store a memory chaining status, a second flip-flop having an initial ''''wired address'''' state, an address register, an address bus, and a data bus, means conditioned by the ''''wired address'''' state of said second flip-flop to supply over said address bus the address of the dedicated counter location to the computer, and over said data bus to receive in said address register the address of a first data address counter, and to change said second flip-flop to an ''''address register'''' state, means conditioned by the ''''address register'''' state of said second flip-flop and using said address bus to successively supply the content of said address register to the computer and using said data bus to successively transfer data words of a block, a third flip-flop conditioned by the ''''address register'''' state of said second flip-flop and an overflow signal received from the computer to assume a ''''word overflow'''' state, means to change the second flip-flop to its ''''wired address'''' state for the supplying of the address of the dedicated counter location to the computer, and to return the second flip-flop to its ''''address register'''' state for the transferring of data words of a next block, a fourth flip-flop conditioned by a ''''wired address'''' state of said second flip-flop and an overflow signal received from the computer to assume a ''''block overflow'''' state, and means responsive to the ''''word overflow'''' and ''''block overflow'''' states of said third and fourth flip-flops to cause a termination of the I/O operation.

Claim 11

A data transfer system, comprising means for storing a plurality of blocks of data words, a plurality of data address counters each initially storing the address of the first data word of a corresponding block of data words, sequential storage locations stOring a list of the addresses of said data address counters in the order in which said blocks of data words are to be transferred, a dedicated counter initially storing the address of the first location of said list of addresses, means using one data address counter at a time to sequentially transfer the data words of the associated block of data words, and means using the dedicated counter and the list of addresses to sequentially access said data address counters for the sequential transferring of said blocks of data words.

Claim 12

A data transfer system, comprising means for storing a plurality of blocks of data words, a plurality of data address counters each initially storing the address of the first data word of a corresponding block of data words, sequential storage locations stOring a list of the addresses of said data address counters in the order in which said blocks of data words are to be transferred, a dedicated counter initially storing the address of the first location of said list of addresses, means using one data address counter at a time to sequentially transfer the data words of the associated block of data words, and means using the dedicated counter and the list of addresses to sequentially access said data address counters for the sequential transferring of said blocks of data words.

Claim 13

A computer input-output system, comprising memory locations for a plurality of blocks of data words, memory locations for a plurality of address counters each initially storing the address of the first data word of a corresponding block of data words, sequential memory locations for a list of the addresses of said data address counters in the order in which said blocks of data words are to be transferred, a memory location for a dedicated counter initially storing the address of the first location of said list of addresses, and computer means using one data address counter at a time to sequentially transfer the data words of the associated block of data words, and using the dedicated counter and the list of addresses to sequentially access said data address counters for the sequential transferring of said blocks of data words.

Claim 14

A computer input-output system, comprising memory locations for a plurality of blocks of data words, memory locations for a plurality of address counters each initially storing the address of the first data word of a corresponding block of data words, sequential memory locations for a list of the addresses of said data address counters in the order in which said blocks of data words are to be transferred, a memory location for a dedicated counter initially storing the address of the first location of said list of addresses, and computer means using one data address counter at a time to sequentially transfer the data words of the associated block of data words, and using the dedicated counter and the list of addresses to sequentially access said data address counters for the sequential transferring of said blocks of data words.

Claim 15

A computer input-output system as defined in claim 9 wherein said computer means includes a processor and an I/O controller connected by a data bus, said I/O controller having means responsive to a first stimulus to discontinue the transferring of data words of a block and transfer data words of a next block, and second means responsive to a second stimulus to terminate the transferring of data words.

Claim 16

A system as defined in claim 10 wherein at least one of said stimuli is an overflow signal received from said processor.

Claim 17

A system as defined in claim 10 wherein at least one of said stimuli is the presence of a predetermined control character on said data bus.

Claim 18

A computer input-output system, comprising an I/O controller, a computer processor, and a computer memory, said memory containing storage locations for: a plurality of blocks of data words, a plurality of counter locations each containing a data address counter for a first data word address of a respective block of data, and a word counter for the number of the words in the block, a list of addresses of said counter locations in the order in which the respective blocks of data are to be transferred, and a dedicated counter location containing a list address counter for the address of the first one of the locations containing said list of addresses, and a block counter for the number of blocks to be transferred; means responsive to a chaining command from said computer to follow an addressing path through the list address counter, the first location in the list of addresses, and a first data address counter to transfer a first data word in a first block of data, each address counter being incremented and each associated word and block counter being decremented after an access, means using the successively-incremented contents of the data address counter to successively transfer data words in the first data block until the successively-decremented word counter signals the end of the data block, means to follow addressing paths through the successively-incremented list address counter, the list of addresses, and data address counters to similarly transfer blocks of data words until the successively-decremented block counter signals the end of the transfer of all blocks of data.

Claim 19

A computer input-output system, comprising an I/O controller, a computer processor, and a computer memory, said memory containing storage locations for: a plurality of blocks of data words, a plurality of counter locations each containing a data address counter for a first data word address of a respective block of data, and a word counter for the number of the words in the block, a list of addresses of said counter locations in the order in which the respective blocks of data are to be transferred, and a dedicated counter location containing a list address counter for the address of the first one of the locations containing said list of addresses, and a block counter for the number of blocks to be transferred; means responsive to a chaining command from said computer to follow an addressing path through the list address counter, the first location in the list of addresses, and a first data address counter to transfer a first data word in a first block of data, each address counter being incremented and each associated word and block counter being decremented after an access, means using the successively-incremented contents of the data address counter to successively transfer data words in the first data block until the successively-decremented word counter signals the end of the data block, means to follow addressing paths through the successively-incremented list address counter, the list of addresses, and data address counters to similarly transfer blocks of data words until the successively-decremented block counter signals the end of the transfer of all blocks of data.

Claim 20

A computer system, comprising a computer having a main memory, the memory having a dedicated counter location dedicated to an I/O controller for addressing sequential memory locations each of which contains the address of a data address counter for sequentially addressIng memory word locations containing a block of data words, an I/O controller including a dedicated counter address source, an address register, a word overflow flip-flop and a block overflow flip-flop, control lines, an address bus, and a data bus connecting the computer and the controller, means in said controller including said dedicated counter address source to supply over said address bus to the computer the address of the dedicated counter location, and to receive in said address register over said data bus the address of a first data address counter, means in said controller including said address register to successively supply over said address bus the content of said address register to the computer, and to successively transfer over said data bus the data words of a block, means in said controller including said word overflow flip-flop operative in response to an overflow signal received from the computer during a data word transfer to again supply the address of the dedicated counter location over said address bus to the computer, and to use said data bus to receive in said address register the address of a next data address counter for use in transferring data words of a next block, and means in said controller including said block overflow flip-flop operative in response to an overflow signal received from the computer during use of said dedicated counter location to subsequently terminate the I/O operation.

Claim 21

A computer system, comprising a computer having a main memory, the memory having a dedicated counter location dedicated to an I/O controller for addressing sequential memory locations each of which contains the address of a data address counter for sequentially addressIng memory word locations containing a block of data words, an I/O controller including a dedicated counter address source, an address register, a word overflow flip-flop and a block overflow flip-flop, control lines, an address bus, and a data bus connecting the computer and the controller, means in said controller including said dedicated counter address source to supply over said address bus to the computer the address of the dedicated counter location, and to receive in said address register over said data bus the address of a first data address counter, means in said controller including said address register to successively supply over said address bus the content of said address register to the computer, and to successively transfer over said data bus the data words of a block, means in said controller including said word overflow flip-flop operative in response to an overflow signal received from the computer during a data word transfer to again supply the address of the dedicated counter location over said address bus to the computer, and to use said data bus to receive in said address register the address of a next data address counter for use in transferring data words of a next block, and means in said controller including said block overflow flip-flop operative in response to an overflow signal received from the computer during use of said dedicated counter location to subsequently terminate the I/O operation.

Claim 22

A computer system as defined in claim 14 wherein said I/O controller also includes a control unit, a read-write flip-flop, and a memory-chaining flip-flop, and means in said controller including said control unit and said read-write and memory-chaining flip-flops to receive commands over said control lines from the computer and to condition the controller for read or write operation with or without memory chaining.