Patent US3728638A successfully refreshed from Google Patents.
US3728638A
Expired / Lapsed
US
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Transistorized power amplifier circuit
Assignee: Hitachi Ltd
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Filing: 1971-07-13
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Granted: 1973-04-17
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Expires: 1991-07-13
Abstract
Abstract A transistorized power amplifier circuit comprises an input transistor circuit capable of class-A amplifier operation according to base input and collector output, a first and a second output transistor, and a diode coupling circuit receiving the collector output from the input transistor circuit as an input signal thereof for alternatively driving the output transistors into conduction at each successive half cycle of the input signal. A DC negative feedback circuit is connected between the output terminal of the output transistors and the emitter of the input transistor, and all the transistors are of the same conduction characteristic.
Inventors
- 👤 K Seki
- 👤 S Okuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:16
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/52; H03F3/00; H03F3/30; H03F3/3083; H03F3/3086; H03F3/3096
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
186 words
A transistorized power amplifier circuit comprising: an input transistor circuit capable of class-A amplifier operation according to base input and collector input including a first transistor and an emitter resistor connected to the emitter of said first transistor; an output transistor circuit capable of class-B amplifier operation including a second and a third transistor of the same conduction characteristic as said first transistor, a first diode means connected between the emitter of said second transistor and the collector of said third transistor, a second and a third diode means connected in series between the base of said second transistor and the collector of said third transistor so as to make said second and third transistors operate in class-B, and an output terminal connected to the emitter of said second transistor; a circuit means for coupling the collector of said first transistor with the base of said third transistor; and a DC negative feedback means connected between the emitter of said second transistor and the emitter of said first transistor so as to maintain the biasing potential of said second and third transistors to a predetermined value.
Claim 2
Dependent Claim
186 words
A transistorized power amplifier circuit comprising: an input transistor circuit capable of class-A amplifier operation according to base input and collector input including a first transistor and an emitter resistor connected to the emitter of said first transistor; an output transistor circuit capable of class-B amplifier operation including a second and a third transistor of the same conduction characteristic as said first transistor, a first diode means connected between the emitter of said second transistor and the collector of said third transistor, a second and a third diode means connected in series between the base of said second transistor and the collector of said third transistor so as to make said second and third transistors operate in class-B, and an output terminal connected to the emitter of said second transistor; a circuit means for coupling the collector of said first transistor with the base of said third transistor; and a DC negative feedback means connected between the emitter of said second transistor and the emitter of said first transistor so as to maintain the biasing potential of said second and third transistors to a predetermined value.
Claim 3
Dependent Claim
51 words
A circuit according to claim 1, wherein said coupling circuit means comprises an emitter-follower transistor circuit having a fourth transistor of the same conduction characteristic as said first transistor with a base connected to the collector of said first transistor and an emitter connected to the base of said third transistor.
Claim 4
Dependent Claim
25 words
A circuit according to claim 1, wherein said feedback means comprises a resistor connected between said output terminal and the emitter of said first transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |