Patent US3728559A successfully refreshed from Google Patents.
US3728559A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hybrid high speed ecl to p-channel mos clock driver
Assignee: Westinghouse Electric Corp
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Filing: 1971-11-26
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Granted: 1973-04-17
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Expires: 1991-11-26
Abstract
Abstract A voltage level shifting circuit which can be used as a high speed MOS clock driver, for example, driven by any emittercoupled, non-saturated logic device. This is achieved, among other things, by the use of transformer coupling which offers isolation, minimal power requirements, and maximum efficiency. At the same time, the circuitry permits hybrid circuit packaging. The circuit has a broad frequency range and minimal rise and fall times for digital signals while feeding into a capacitive load.
Inventors
- 👤 J Spann
- 👤 J Gentry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/601
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
156 words
Circuit apparatus for converting pulses of one frequency and voltage level into pulses of the same frequency but different voltage level, comprising a pair of input transistors having their emitters connected to a source of reference potential, a transformer having a primary winding and a pair of secondarY windings, means connecting the collectors of said input transistors to the opposite ends of said primary winding, means connecting a center tap on said primary winding to a source of driving potential, a pair of output transistors having their emitters and collectors connected in series between said point of reference potential and said source of driving potential, means connecting one of said secondary windings between the base and emitter of one of said output transistors, means connecting the other of said secondary windings between the base and emitter of the other of said output transistors, and means for deriving an output from the junction between said output transistors.
Claim 2
Dependent Claim
156 words
Circuit apparatus for converting pulses of one frequency and voltage level into pulses of the same frequency but different voltage level, comprising a pair of input transistors having their emitters connected to a source of reference potential, a transformer having a primary winding and a pair of secondarY windings, means connecting the collectors of said input transistors to the opposite ends of said primary winding, means connecting a center tap on said primary winding to a source of driving potential, a pair of output transistors having their emitters and collectors connected in series between said point of reference potential and said source of driving potential, means connecting one of said secondary windings between the base and emitter of one of said output transistors, means connecting the other of said secondary windings between the base and emitter of the other of said output transistors, and means for deriving an output from the junction between said output transistors.
Claim 3
Dependent Claim
33 words
The apparatus of claim 1 wherein the secondary windings of said transformer are connected between the base and emitter of the respective output transistors such that the transistors cannot be turned ON simultaneously.
Claim 4
Dependent Claim
41 words
The apparatus of claim 2 wherein the bases of the respective output transistors are of the same conductivity-type material and said secondary windings are connected to the respective bases such that the polarities of the voltages thereon will always be reversed.
Claim 5
Dependent Claim
65 words
The apparatus of claim 1 wherein the emitter of one of said output transistors is connected to said source of driving potential, the collector of the other output transistor is connected to said point of reference potential, the collector of said one output transistor and the emitter of the other output transistor being interconnected, and the output being taken from said interconnected emitter and collector.
Claim 6
Dependent Claim
21 words
The apparatus of claim 1 including a capacitor connected between the mid-tap on said primary winding and a source of potential.
Claim 7
Dependent Claim
23 words
The apparatus of claim 1 wherein all of the circuit elements recited therein including said transformer are mounted on a single nonconductive substrate.
Claim 8
Dependent Claim
15 words
The apparatus of claim 6 wherein said transformer is wound on a ferrite memory core.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |