Patent US3728532A successfully refreshed from Google Patents.
US3728532A
Expired / Lapsed
US
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Carry skip-ahead network
Assignee: RCA Corp
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Filing: 1972-01-21
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Granted: 1973-04-17
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Expires: 1992-01-21
Abstract
Abstract A network for use with arithmetic units such as adder circuits wherein a large number of bits are added together. Provision is made for evaluating the added bits in conjunction with the carryin signal supplied to the adder so that the carry signal may be ''''skipped ahead,'''' i.e. passed over, one or more adder circuit segments in order to avoid the delay of propagating a carry signal through each adder circuit segment in the arithmetic unit.
Inventors
- 👤 R Pryor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
131 words
In combination, a plurality of adder ciRcuit stages, each of said adder circuit stages including sum logic circuit means for producing a sum output signal, each of said adder circuit stages including carry logic circuit means for producing a carry output signal, gate means connected to the sum logic circuit means pf certain adjacent adder circuit stages to produce an output signal indicative of the signal conditions at the associated said sum logic circuit means, and circ it means connected to said gate means to receive the output signal therefrom and to selectively connect the carry input of the carry logic circuit means of the first of said certain adder circuit stages to the output of the carry logic circuit means in the last of said certain adjacent adder circuit stages.
Claim 2
Dependent Claim
131 words
In combination, a plurality of adder ciRcuit stages, each of said adder circuit stages including sum logic circuit means for producing a sum output signal, each of said adder circuit stages including carry logic circuit means for producing a carry output signal, gate means connected to the sum logic circuit means pf certain adjacent adder circuit stages to produce an output signal indicative of the signal conditions at the associated said sum logic circuit means, and circ it means connected to said gate means to receive the output signal therefrom and to selectively connect the carry input of the carry logic circuit means of the first of said certain adder circuit stages to the output of the carry logic circuit means in the last of said certain adjacent adder circuit stages.
Claim 3
Dependent Claim
90 words
The combination recited in claim 1 wherein said sum logic circuit means includes first and second exclusive OR gates, each having two input terminals and an output terminal, said input terminals of said first OR gate connected to receive addend and augend signals, respectively, said input terminals of said second OR gate connected to receive the carry-in signal from a previous stage, and the output signal from said first exclusive OR gate respectively, said second exclusive OR gate operative to produce the sum output signal on the output terminal thereof.
Claim 4
Dependent Claim
93 words
The combination recited in claim 1 wherein said carry logic means includes switch means having two input terminals, a control terminal and an output terminal, one of said input terminals connected to receive one of the addend or augend signals supplied to the adder circuit stage, the other input terminal connected to receive the carry-in signal supplied to the adder circuit stage, and the control terminal connected to said sum logic circuit to receive a signal therefrom representative of the relation between the addend and augend signals supplied to the adder circuit stage.
Claim 5
Dependent Claim
32 words
The combination recited in claim 2 wherein said gate means is connected to receive signals from the outputs of the first exclusive OR gates in at least two adjacent adder circuit stages.
Claim 6
Dependent Claim
34 words
The combination recited in claim 4 wherein said circuit means comprises switch means connected to said gate means, said switch means being selectively rendered conductive in response to a signal from said gate means.
Claim 7
Dependent Claim
87 words
The combination recited in claim 5 wherein said switch means includes a pair of opposite conductivity type semiconductor devices, having the conduction paths thereof connected in parallel one end of said parallel connected conduction paths connected to an input of said carry logic circuit means of the first one of said certain adjacent adder circuit stages and the other end of said parallel connected conduction paths connected to the output of said carry logic circuit means in the last one of said certain adjacent adder circuit stages.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |