Zero crossing detecting circuit

Claim 2

In a digital data detection system in which zero crossings of a data signal are detected and a bistable device is normally switched in response to each detection of a zero crossing to provide a representation of the data signal, the improvement comprising means responsive to each zero crossing of the representation of the data signal as denoted by switching of the bistable device for producing an output signal of selected duration, and means responsive to each output signal for preventing switching of the bistable device during the duration of the output signal.

Claim 3

The invention defined in claim 1, wherein the duration of each output signal is chosen so as to encompAss zero crossings produced by high frequency noise signals superimposed on the data signal.

Claim 4

The invention defined in claim 2, wherein the data signal comprises a phase encoded signal, and each output signal has a duration approximately equal to one-tenth the length of a bit interval of the data signal.

Claim 5

An arrangement for detecting zero crossings of a data signal comprising: means responsive to the data signal for providing an indication upon the occurrence of each zero crossing in the data signal; bistable means; logic means coupled to the bistable means and operative to change the state of the bistable means in response to each zero crossing indication except when inhibited; pulse generating means coupled to the bistable means for generating a pulse in response to each change of state of the bistable means; and means coupling the pulse generating means to the logic means to inhibit the logic means in response to each generated pulse.

Claim 6

An arrangement for detecting zero crossings of a data signal comprising: means responsive to the data signal for providing an indication upon the occurrence of each zero crossing in the data signal; bistable means; logic means coupled to the bistable means and operative to change the state of the bistable means in response to each zero crossing indication except when inhibited; pulse generating means coupled to the bistable means for generating a pulse in response to each change of state of the bistable means; and means coupling the pulse generating means to the logic means to inhibit the logic means in response to each generated pulse.

Claim 7

The invention defined in claim 4, wherein the logic means comprises first and second logical elements intercoupled to provide alternate outputs in response to each zero crossing indication when enabled, and means for enabling the first and second logical elements except during the occurrence of a generated pulse.

Claim 8

The invention defined in claim 5, wherein the enabling means includes means for delaying the enabling of the second logical element for a selected period of time after termination of a generated pulse.

Claim 9

The invention defined in claim 5, wherein the bistable means comprises third and fourth logical elements cross-coupled with one another to provide alternate outputs and responsive to the outputs of respective ones of the first and second logical elements.

Claim 10

The invention defined in claim 7, wherein the data signal is divided into successive bit intervals, and the pulse generating means includes means responsive to a change in the output of either of the third and fourth logical elements for generating a pulse having a width bearing a selected relation to the length of the bit intervals.

Claim 11

A circuit for detecting zero crossings of a data signal comprising: comparator means for comparing the data signal to a zero crossing reference to produce a change in the bilevel output thereof each time the data signal equals the zero crossing reference; a latching circuit comprising first and second NAND circuits cross-coupled such that the output of each is coupled as an input to the other; pulse generating means coupled to the outputs of the first and second NAND circuits and operative to generate a pulse of predetermined duration each time one of the outputs of the first and second NAND circuits changes in a given sense; means coupled to the pulse generating means for providing an enabling signal at an output thereof except during the generation of a pulse; a third NAND circuit having inputs coupled to the outputs of the comparator means and the enabling signal means and an output coupled as an input of the first NAND circuit; and a fourth NAND circuit having inputs coupled to the outputs of the third NAND circuit and the enabling signal means and an output coupled as an input of the second NAND circuit.

Claim 12

A circuit for detecting zero crossings of a data signal comprising: comparator means for comparing the data signal to a zero crossing reference to produce a change in the bilevel output thereof each time the data signal equals the zero crossing reference; a latching circuit comprising first and second NAND circuits cross-coupled such that the output of each is coupled as an input to the other; pulse generating means coupled to the outputs of the first and second NAND circuits and operative to generate a pulse of predetermined duration each time one of the outputs of the first and second NAND circuits changes in a given sense; means coupled to the pulse generating means for providing an enabling signal at an output thereof except during the generation of a pulse; a third NAND circuit having inputs coupled to the outputs of the comparator means and the enabling signal means and an output coupled as an input of the first NAND circuit; and a fourth NAND circuit having inputs coupled to the outputs of the third NAND circuit and the enabling signal means and an output coupled as an input of the second NAND circuit.

Claim 13

The invention defined in claim 9, wherein the pulse generating means comprises a pair of pulse generators, each being responsive to the output of a different one of the first and second NAND circuits, and the enabling signal means comprises a NOR circuit having separate inputs coupled to the outputs of the pair of pulse generators.

Claim 14

The invention defined in claim 10, wherein each of the pair of pulse generators comprises a normally conducting transistor which is coupled to be biased into non-conduction upon change of the output of the associated one of the first and second NAND circuits in the given sense, and a resistor-capacitor circuit coupled to the transistor for maintaining non-conduction of the transistor foR a period of time equal to the predetermined pulse duration.