Abstract A method is disclosed for detecting address line failures employing a series of three tests. A first test is performed to determine whether a first group of address bit lines have failed resulting in an indication of an access to a location beyond the limits of the storage system. A second series of tests is performed to determine whether any address line has become shortcircuited so as to always indicate a logic 1 resulting in an error indication. A third series of tests is performed to determine whether any address line is opened resulting in the continual presence of a logic 0. The tests are performed sequentially on all address lines accessing the storage system up to and including the last address to be tested in the system.
A method of detecting address line failures in a single select line storage system comprising the steps of: storing in each storage location data representative of an address for said location; reading from each location the data stored in said location; comparing data stored in each said location with data read from each said location to determine if a data pattern indicating an access beyond the limits of said system has been received; second testing for short-circuited address lines by storing an all zero''s data pattern to detect any erroneous one bits; third testing for open-circuited address lines by storing all one''s data to detect any erroneous zero bits.
Claim 2
Independent Claim
109 words
A method of detecting address line failures in a single select line storage system comprising the steps of: storing in each storage location data representative of an address for said location; reading from each location the data stored in said location; comparing data stored in each said location with data read from each said location to determine if a data pattern indicating an access beyond the limits of said system has been received; second testing for short-circuited address lines by storing an all zero''s data pattern to detect any erroneous one bits; third testing for open-circuited address lines by storing all one''s data to detect any erroneous zero bits.
Claim 3
Dependent Claim
60 words
A method according to claim 1 wherein said step of second testing comprises: storing in each storage location data representative of an all zero''s pattern; reading data from each storage location; comparing said data read to determine if any one bits are present; indicating an error on the address line for the storage location which indicated a one bit present.
Claim 4
Dependent Claim
65 words
A method according to claim 2 wherein said step of third testing comprises: storing all one''s data in each storage location; reading data from each storage location; comparing said data read from each storage location to determine if any zero bits, indicating a dropped bit, are present; indicating an error on the address line for the storage location at which the dropped bit was indicated.
Claim 5
Dependent Claim
34 words
A method according to claim 1 further comprising the steps of: disabling any error checking circuitry responsive to errors in said storage system to prevent erroneous error indication due to unverified error checking circuits.