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US3726002A
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Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate
Assignee: International Business Machines Corp
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Filing: 1971-08-27
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Granted: 1973-04-10
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Expires: 1991-08-27
Abstract
Abstract A process for fabricating a high performance electrical interconnection package for a plurality of semiconductor chips including the steps of selecting an appropriate dissimilar refractory substrate, forming a plurality of bubble-free layers of glass over the substrate, depositing a plurality of planar metallization patterns on each layer of deposited glass, selectively depositing vertical studs for electrical interconnection between various conductive patterns, and bonding a plurality of integrated circuit chips to the upper surface of the glass package.
Inventors
- 👤 B Greenstein
- 👤 M Turetzky
- 👤 P Langston
- 👤 B Narken
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:10
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4644; H05K3/4647; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W70/69; H05K1/00; H05K1/02; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09509; H05K2203/00; H05K2203/07; H05K2203/0703; H05K2203/0733; H05K3/10; H05K3/108; H05K3/20; H05K3/205; H05K3/22; H05K3/24; H05K3/243; H05K3/4664; H05K3/4667; H05K3/467; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/251; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144; Y10T29/49155; Y10T29/49158; Y10T29/4916
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
58 words
A method for fabricating a high performance solid glass-metal electrical interconnection package adaptable for bonding to a plurality of semiconductor integrated circuit chips as in claim 1 further including the steps of: a. fabricating as many desired levels or metallized conductive planes by sequentially and successively depositing a metallized conductive pattern on the uppermost glass layer surface by,
Claim 2
Dependent Claim
26 words
depositing a glass slurry over the uppermost glass layer surface, and then firing, cooling, and conditioning the upper surface of the new resulting uppermost glass layer.
Claim 3
Dependent Claim
60 words
A method for fabricating a high performance solid glass-metal electrical interconnection package adaptable for bonding to a plurality of semiconductor integrated circuit chips as in claim 2 further including the steps of: a. depositing a metallized pattern on the resulting uppermost glass layer surface, b. bonding a plurality of semiconductor chips to the resulting uppermost glass layer surface metallized pattern.
Claim 4
Dependent Claim
158 words
A method for fabricating a high performance solid glass-metal electrical interconnection package adaptable for bonding to a plurality of semiconductor integrated circuit chips as in claim 1 wherein the steps of depositing said first and second metallized conductive patterns and said plurality of conductive studs on said substrate and said first glass layer further comprise the steps of: a. depositing a plurality of overlying metal layers for forming said metallized conductive patterns and selecting the uppermost layer for providing a superior bonding surface for said studs and the next-to-uppermost layer for providing superior adhesion properties to the selected glass composition, b. selectively removing layers of said metallized conductive pattern for defining an electroplating terminal and an electrical interconnection-path, c. electroplating said conductive studs on said uppermost metal layer using said electroplating terminal, d. removing said electroplating terminal, and e. removing selectively the uppermost layer of said metal for exposing the next-to-uppermost layer having good adhesion properties to glass.
Claim 5
Dependent Claim
81 words
A method for fabricating a high performance solid glass-metal electrical interconnection package adaptable for bonding to a plurality of semiconductor integrated circuit chips comprising the steps of claim 1 wherein the step of conditioning the first glass layer upper surface further includes the step of: a. removing excessive glass material to a predetermined first glass layer thickness for providing a planar glass layer surface with the exposed stud ends residing in the same plane, and for providing desired dielectric impedance value.
Claim 6
Dependent Claim
52 words
A method for fabricating a high performance solid glass-metal electrical interconnection package adaptable for bonding to a plurality of semiconductor integrated circuit chips as in claim 4 wherein the step of depositing a plurality of overlying metal layer includes the step of: a. sequentially depositing chrome, copper, chrome, and copper metal layers.
Claim 7
Dependent Claim
64 words
A method for fabricating a high performance solid glass-metal electrical interconnection package adaptable for bonding to a plurality of semiconductor integrated circuit chips as in claim 1 wherein the step of providing a substrate further includes the step of: a. selecting a substrate of dissimilar refractory material, having a thermal coefficient of expansion higher than that of said first and second Layers of glass.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-09 | 1976-10-09 | 1977-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-09 | 1980-10-09 | 1981-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-09 | 1984-10-09 | 1985-04-10 | $7700.00 | Window Closed / Lapsed |