US3725878A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell circuit
Assignee: International Business Machines Corp
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Filing: 1970-10-30
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Granted: 1973-04-03
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Expires: 1990-10-30
Abstract
Abstract A memory cell circuit is provided with a plurality of cells arranged in rows and columns. Each cell comprises a pair of cross-coupled transistors with the collector of each transistor direct-coupled to the base of the other transistor Each transistor has a pair of emitters. One emitter of each pair is connected in a current-switch mode with the emitters of the sense amplifier transistors.
Inventors
- 👤 A Berding
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/411; G11C11/4116; G11C11/416; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A memory circuit comprising a matrix of memory cells arranged in rows and columns, each cell including a pair of transistors each having an emitter and a collector connected to a base of the other transistor of the pair, a plurality of pairs of writing transistors each having an emitter, each pair of writing transistors being associated with a respective column of memory cells, means connecting said emitter of one transistor of every cell in each column of cells to the emitter of one writing transistor of the respective associated pair of writing transistors for coaction of said writing transistor and said cell transistors in a current switch mode, and means connecting said emitter of the other transistor of every cell in each column of cells to the emitter of the other writing transistor of the respective associated pair of writing transistors for coaction of said other writing transistor and said cell transistors connected thereto in a current switch mode.
Claim 2
Dependent Claim
160 words
A memory circuit comprising a matrix of memory cells arranged in rows and columns, each cell including a pair of transistors each having an emitter and a collector connected to a base of the other transistor of the pair, a plurality of pairs of writing transistors each having an emitter, each pair of writing transistors being associated with a respective column of memory cells, means connecting said emitter of one transistor of every cell in each column of cells to the emitter of one writing transistor of the respective associated pair of writing transistors for coaction of said writing transistor and said cell transistors in a current switch mode, and means connecting said emitter of the other transistor of every cell in each column of cells to the emitter of the other writing transistor of the respective associated pair of writing transistors for coaction of said other writing transistor and said cell transistors connected thereto in a current switch mode.
Claim 3
Dependent Claim
34 words
A memory circuit as set forth in claim 1 wherein each of said cell transistors has a second emitter, and a current source connected to the second emitters of each pair of cell transistors.
Claim 4
Dependent Claim
80 words
A memory circuit as set forth in claim 1 and comprising a plurality of sensing transistors each having an emitter and each associated with a respective column of cells, means connecting said emitter of each sensing transistor to the emitter of one of the writing transistors associated with the respective column of cells for coaction of said sensing transistor, writing transistor and cell transistors in a current switch mode, and means associated with each sensing transistor for detecting current therethrough.
Claim 5
Dependent Claim
34 words
A memory circuit as set forth in claim 3 wherein each of said cell transistors has a second emitter, and a current source connected to the second emitters of each pair of cell transistors.
Claim 6
Dependent Claim
101 words
A memory circuit comprising a matrix of memory cells arranged in rows and columns, each cell including a pair of transistors each having an emitter and a collector connected to a base of the other transistor of the pair, a plurality of sensing transistors each having an emitter and each associated with a respective column of cells, means connecting in a current switch mode said emitter of each sensing transistor to the emitter of only one of the cell transistors of all cells of the respective associated column of cells, and means associated with each sensing transistor for detecting current therethrough.
Claim 7
Dependent Claim
101 words
A memory circuit comprising a matrix of memory cells arranged in rows and columns, each cell including a pair of transistors each having an emitter and a collector connected to a base of the other transistor of the pair, a plurality of sensing transistors each having an emitter and each associated with a respective column of cells, means connecting in a current switch mode said emitter of each sensing transistor to the emitter of only one of the cell transistors of all cells of the respective associated column of cells, and means associated with each sensing transistor for detecting current therethrough.
Claim 8
Dependent Claim
34 words
A memory circuit as set forth in claim 5 wherein each of said cell transistors has a second emitter, and a current source connected to the second emitters of each pair of cell transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |