Means and method for time-sharing multichannel well logging

Claim 2

A well logging system for providing a plurality of outputs corresponding to different conditions sensed in a borehole, comprising a logging instrument including means for providing pulse signals, each pulse signal being representative of a different condition sensed in the borehole, a plurality of counters connected to the pulse signal means, each counter counting the pulses in a different pulse signal, and means connected to the counters for providing a pulse train, each cycle of the pulse train being divided into predetermined time intervals and the number of pulses occurring in a predetermined time interval is the complement of a count in a corresponding counter; means connected to pulse train means in the logging instrument for transmitting the pulse train; and surface electronics adjacent to the borehole including means connected to the transmitting means for separating the pulses in the pulse train according to the predetermined time intervals, and output means connected to the separating means, each output means receiving the pulses in the pulse train for a different time interval for providing an output corresponding to a sensed condition in accordance with the pulses from the separating means.

Claim 3

A system as described in claim 1 in which the pulse train means include a source of timing pulses, means for providing control pulses, each control pulse occurs during a different predetermined time interval, and switching means, each switching means being connected to the source of timing pulses, to a corresponding counter, to the control pulse means and to the transmission system and controlled by the output from the counter and a control pulse from the control pulse means to pass timing pulses to the transmission system and to the counter during a predetermined time interval until the counter reaches a predetermined count so that the number of timing pulses passed by the swItching means corresponds to the complement of the count in the counter and to block the timing pulses during the absence of a control pulse or during the presence of the predetermined count in the counter.

Claim 4

A system as described in claim 2 in which the pulse train means includes reset means periodically providing a reset pulse.

Claim 5

A system as described in claim 3 in which each cycle of the pulse train includes one more time interval, and the pulse train means includes means for providing a synchronizing pulse during the last mentioned time interval.

Claim 6

A system as described in claim 4 in which the pulse train means also includes counting means connected to the reset means and being periodically reset by the reset pulse, each counting means being connected to corresponding sensing means and counting the condition pulses therefrom, a source of timing pulses, means for providing a plurality of control signals, and first switching means connected to the separating means, to the counting means and to the control signal means, and responsive to the control signals from the control signal means to pass the timing pulses to different counting means and to the separating means during each time interval until the counting means controls the first switching means to block the timing pulses when a predetermined count is reached so that the timing pulses provided to the seperating means in any time interval correspond to the predetermined count less the count of the pulses from the corresponding sensing means.

Claim 7

A system as described in claim 5 in which the synchronizing pulse means includes a flip-flop connected to the reset means and being changed to one state by a reset pulse from the reset means and providing an output, while the flip-flop is in the one state, and providing no output while the flip-flop is in another state, a NAND gate connected to the flip-flop, to the control signal means and to the timing pulse source and controlled by the presence of a control signal from the control signal means and the absence of an output from the flip-flop to pass a timing pulse from the timing pulse source to the flip-flop causing the flip-flop to change from the one state to the other state, and controlled by the absence of a control signal from the control signal means or the presence of an output from the flip-flop to block the timing pulses from the timing pulse source, and a monostable multivibrator connected to the last mentioned NAND gate and to the conductor and responsive to the passed timing pulse from the last mentioned NAND gate for providing a synchronizing pulse having a substantially larger amplitude than the timing pulses from the timing pulse source.

Claim 8

A system as described in claim 5 in which the separating means includes a separator network for separating synchronizing pulses from the other pulses in the pulse train, second means for providing a plurality of control signals, each control signal occurring during a different time interval, third means for providing a plurality of control signals, each control signal from the third control signal means being delayed in time by a predetermined amount from a corresponding control signal from the second control signal means, and second switching connected to the first switching means to the control signal means and to the output means and being controlled by the control signals from the second control signal means to pass the pulse train from the first switching means to different output means during each time interval so as to separate the pulses in the pulse train according to time interval.

Claim 9

A system as described in claim 9 further comprising a second source of timing pulses, and in which each output means includes counting means connected to the third control signal means, to the second switching means and to the second timing pulse source and counting the pulses passed by the second switching means during a particular time interval of each cycle of the pulse train from the first switching meanS and controlled by a control signal from the third control signal means to simultaneously count and pass timing pulses from the second timing pulse source as an output corresponding to a condition until a predetermined count of the pulses from the second switching means and the second timing pulse source is reached.

Claim 10

A system as described in claim 5 in which the switching means includes a plurality of NAND gates, each NAND gate being connected to the timing pulse source, to the control signal means, to the separating means and to corresponding counting means and controlled by the control signal means and the counting means to pass the timing pulses during a particular time interval to the separating means and to the counting means until the predetermined count is reached by the counting means, and to block the timing pulses during the remainder of the time interval and during any other time interval.

Claim 11

A system as described in claim 9 in which each counting means includes an OR gate connected to corresponding sensing means and to a corresponding NAND gate for passing the condition pulses from the sensing means and the passed timing pulses from the NAND gate, and a counter connected to the OR gate, to the NAND gate and to the reset means for providing a direct current output of one level to the NAND gate while counting the pulses passed by the OR gate until the predetermined count is reached at which time the counter provides a direct current output of another level to the NAND gate so as to disable the NAND gate until the counter is reset by a reset pulse from the reset means.

Claim 12

A system as described in claim 5 in which the timing pulse source provides control pulses at the same rate but differing in time from the other pulses; and control signal means includes means connected to the timing pulse source and to the reset means and providing a pulse train whose pulses coincide with the start of each time interval, except for the time interval, in accordance with the control pulses from the timing source and the reset pulse from the reset means, and a plurality of flip-flops connected to the reset means and connected in series to the last mentioned pulse train so that the flip-flop connected to the last mentioned pulse train means is reset to one state while the other flip-flops are reset to another state by the reset pulse from the reset means, the flip-flop connected to the last mentioned pulse train means changes from the one state to the other state in response to a first pulse in the pulse train from the last mentioned pulse train means, each flip-flop of the other flip-flops changes from the other state to the one state in response to a pulse in the pulse train from the last mentioned pulse train means occurring while the preceding flip-flop is in the one state and changing back to the other state in response to the next pulse in the pulse train from the last mentioned pulse train means, and each flip-flop of the plurality of flip-flops remaining in the other state after changing from the one state until reset by a reset pulse from the reset means and providing a control signal while in the one state and providing no control signal while in the other state.

Claim 13

A system as described in claim 11 in which the reset pulse means includes a monostable multivibrator connected to the last flip-flop of the series connected flip-flops in the control means and responsive to its control signal to provide a pulse output, a differentiating circuit for providing positive and negative spike pulses in response to the pulse from the monostable multivibrator, and amplifying means connected to the differentiating circuit and biased by a direct current voltage so as to amplify only the positive spike pulse to provide the reset pulse.

Claim 14

A system as described in claim 11 in which the last mentioned pulse train means includes a counter connected to the timing pulse source and to the reset means and being reset by the reset pulse from the reset means, and pRoviding a direct current output which alternately changes from one level to another level in response to every fourth control pulse after being reset, a flip-flop receiving a positive direct current voltage and being connected to ground, to the reset means, and to a first stage of the counter and providing a direct current output which changes from a low level to a higher level in response to a change in the direct current output from a first stage of the counter resulting from the counting of the second control pulse from the timing pulse source after being reset by a reset pulse from the reset means, a pair of differentiating circuits, one differentiating circuit being connected to the third stage of the counter and differentiating the output from the third stage of the counter to provide a positive spike pulse when the output from the third stage of the counter changes from a low level to a higher level and a negative spike pulse when the output from the third stage of the counter changes from the higher level to the low level; the other differentiating circuit being connected to the last mentioned flip-flop and differentiating the output from the last mentioned flip-flop to provide a positive spike pulse when the last mentioned flip-flop changes state, and an OR gate connected to the differentiating circuits for inverting and passing the positive spike pulses from the differentiating circuits and blocking the negative spike pulses.

Claim 15

A system as described in claim 13 in which the sensing means and the first mentioned pulse train means are inserted in a borehole having a casing, and one of the sensing means and one of the counting means are used to detect collars in the casing of the borehole.

Claim 16

A system as described in claim 14 in which the reset pulse means further includes a manually operable rotary switch connected to some of the series connected flip-flops and which may be set to a predetermined position to select one of the control signals as the control signal that triggers the monostable multivibrator so as to control the number of time intervals in a cycle and the number of conditions to be sensed.

Claim 17

A system as described in claim 4 in which the separating means includes a separator network for separating the synchronizing pulses from the other pulses in the pulse train from the pulse train means to provide data pulses and synchronization pulses, first means for providing a plurality of control signals, each control signal occurring during a different time interval, second means for providing a plurality of control signals, each control signal from the second control signal means being delayed in time by a predetermined amount from a corresponding control signal from the first control signal means, and switching means connected to the pulse train means and to the control signal means and having a plurality of output terminals and controlled by the control signals to pass the pulse train to a different output terminal during each time interval so as to separate the pulses in the pulse train according to time interval.

Claim 18

A system as described in claim 16 in which the separating means includes means connected to the separator network for providing a delayed synchronization pulse which is delayed in time from the synchronization pulse from the separator network.

Claim 19

A system as described in claim 17 in which the separating means further includes a NAND gate connected to the timing pulse source for passing the timing pulses in the other train from the timing pulse source during the absence of a control voltage and blocking the timing pulses during the presence of a control voltage, a counter connected to the amplifier in the separating means and to the NAND gate which is reset by the synchronization pulse from the amplifier and counting the passed timing pulses from the NAND gate to provide an output when a predetermined count is reached, a differentiating circuit connected to the counter and differentiating the output from the counter to provIde a positive and a negative spike pulse, switching means connected to the differentiating circuit for passing one of the spike pulses from the differentiating circuit as a delayed synchronization pulse and blocking the other spike pulse, a flip-flop connected to the counter, to the NAND gate and to the amplifier of the separating means and being reset to one state by the synchronization pulse from the amplifier to provide no control voltage and changing to another state in response to an output from the counter to provide a control voltage to the NAND gate until reset by the next synchronization pulse so as to prevent the counter from counting after the predetermined count has been reached until the next synchronization pulse.

Claim 20

A system as described in claim 17 in which each control signal means includes counting means connected to the timing pulse source for counting the timing pulses in the one train from the timing pulse source to provide a pulse train whose pulses coincide with the start of each time interval, except the synchronizing pulse time interval, a plurality of flip-flops connected in series to the counting means, and the flip-flop connected to the counting means is reset to one state, while the other flip-flops are reset to another state, the flip-flop connected to the counting means changes from the one state to the other state in response to a first pulse in the pulse train from the counting means, each flip-flop of the other flip-flops changes from the other state to the one state in response to a pulse in the pulse train from the counting means occurring when a preceding flip-flop is in the one state and changing back to the other state in response to the next pulse in the pulse train from the counting means, each flip-flop remaining in the other state after changing from the one state until reset and providing a control signal while in the one state and providing no control signal while in the other state; and the counting means of the first control signal means is periodically preset to another predetermined count by the synchronization pulse and the flip-flops of the first control signal means are periodically reset by the synchronization pulses from the separator network, while the counting means of the second control signal means is periodically preset to the last mentioned predetermined count by the delayed synchronization pulses and the flip-flops of the second control signal means are periodically reset by the delayed synchronization pulses.

Claim 21

A system as described in claim 19 in which the first control signal means includes switching means connecting some of the flip-flops to the reset means for controlling the reset means so as to control the number of time intervals in each cycle of the pulse train from the pulse train means.

Claim 22

A system as described in claim 20 in which the second and third control signal means each include switching means connecting a last flip-flop of the plurality of flip-flops to some of the other flip-flops for controlling the number of control signals.

Claim 23

A system as described in claim 16 in which the synchronizing pulses have substantially larger amplitudes than the other pulses in the pulse train from the pulse train means, and the separator network uses the difference in amplitude to separate the synchronizing pulses from the other pulses in the pulse train.

Claim 24

A system as described in claim 22 in which the separator network includes first and second comparators connected to the pulse train means, the first comparator receiving a direct current reference voltage whose amplitude is less than the amplitudes of the pulses in the pulse train and providing an output when a pulse occurs in the pulse train and providing no output when there is no pulse in the pulse train from the pulse train means, and the second comparator receiving a direct current reference voltage whose amplitude is less than the amplitude of the synchronizing pulses but greater than the amplitudes of the other pulses in the pulse traIn and providing an output when a synchronizing pulse occurs in the pulse train and providing no output when a synchronizing pulse does not occur in the pulse train, first and second monostable multivibrators connected to the first and second comparators, respectively, each multivibrator being responsive to an output from its corresponding comparator to provide a pulse, a differentiating circuit connected to the first multivibrator for differentiating the pulses from the first multivibrator to provide positive and negative spike pulses, an inverter connected to the second multivibrator for inverting the pulses from the other multivibrator, and an AND gate connected to the differentiating circuit and to the inverter for passing the positive spike pulses during the absence of an inverted pulse from the inverter and blocking the spike pulses during the presence of an inverted pulse from the inverter so as to provide a data pulse whenever a pulse, other than a synchronizing pulse, occurs in the pulse train from the pulse train means.

Claim 25

A system as described in claim 23 in which a separator network further includes a third monostable multivibrator connected to the second multivibrator and responsive to a pulse from the second multivibrator to provide a pulse, a source providing two trains of timing pulses having the same repetition rate, the timing pulses of one train differing in time from the timing pulses of the other train, a second AND gate connected to the third multivibrator and to the timing pulse source for passing a timing pulse when the third multivibrator provides a pulse and for blocking the timing pulses when the third multivibrator provides no pulse, a second inverter connected to the second AND gate for inverting the passed pulses from the second AND gate, and an amplifier connected to the inverter for amplifying the inverted pulses to provide synchronization pulses coinciding with the synchronizing pulses in the pulse train from the pulse train means.

Claim 26

A system as described in claim 24 in which each output means includes counting means connected to the second control signal means, to the switching means and to the timing pulse source for counting pulses passed by the switching means of the separator circuit during a particular time interval of each cycle of the pulse train from the pulse train means, and controlled by a control signal from the second control signal means to simultaneously count and pass timing pulses in the other train from the timing pulse source as an output corresponding to a condition, until a predetermined number of pulses from the switching means of the separator network and the timing pulse source has been counted.

Claim 27

A system as described in claim 25 in which the counting means in each output means resets itself after the termination of the control signal applied to the counting means from the second control signal means.

Claim 28

A system as described in claim 26 in which the counting means in each output means includes a flip-flop initially in one state and providing a low level direct current voltage while in that state, and high level direct current voltage while in another state, a NAND gate connected to the timing pulse source, to the second control signal means, and to the flip-flop for passing the timing pulses in the other train from the timing pulse source as an output corresponding to a condition in response to a control signal from the second control signal means and a low level direct current voltage from the flip-flop and blocking the timing pulses in response to high level direct current voltage from the flip-flop or during the absence of a control signal from the second control signal means, an OR gate connected to the switching means of the separator circuit and to the NAND gate for passing the pulses passed by the switching means during a particular time interval of each cycle of the pulse train from the pulse train means and the pulses passed by the NAND gate, a counter connected to the flip-flop aNd to the OR gate for counting the pulses passed by the OR gate and providing an output to the flip-flop when a predetermined count is reached triggering the flip-flop to another state thereby causing the NAND gate to block the timing pulses in the other train from the timing pulse source, and an amplifier connected between the second control signal means and the flip-flop for amplifying the control signal from the second control signal means so that the trailing edge of the control signal resets the flip-flop to the one state.

Claim 29

A method as described in claim 28 in which the pulse train providing step includes providing timing pulses, adding the timing pulses to one of the counts during one of the predetermined time intervals until the count reaches a predetermined value, passing the timing pulses being added to the count to surface as the pulse train so that the number of passed timing pulses is the complement of the count, and repeating the next previous two steps for each of the remaining counts.

Claim 30

A well logging method for providing a plurality of outputs corresponding to different conditions sensed in a borehole, which comprises the steps of providing a plurality of pulse signals in the borehole, each pulse signal being representative of a different condition sensed in the borehole; counting the pulses in each pulse signal in the borehold to provide different counts; providing a pulse train being divided into predetermined time intervals and the number of pulses in a predetermined time interval is the complement of a corresponding count; separating the pulses In the pulse train at the surface according to the predetermined time intervals, and providing the plurality of outputs, each output corresponding to a sensed condition in accordance with the separated pulses for a particular predetermined time interval.

Claim 31

A well logging method for providing a plurality of outputs corresponding to different conditions sensed in a borehole, which comprises the steps of providing a plurality of pulse signals in the borehole, each pulse signal being representative of a different condition sensed in the borehole; counting the pulses in each pulse signal in the borehold to provide different counts; providing a pulse train being divided into predetermined time intervals and the number of pulses in a predetermined time interval is the complement of a corresponding count; separating the pulses In the pulse train at the surface according to the predetermined time intervals, and providing the plurality of outputs, each output corresponding to a sensed condition in accordance with the separated pulses for a particular predetermined time interval.

Claim 32

A method as described in claim 29 in which the step of providing a pulse train includes a plurality of steps, each step comprises providing timing pulses during a different time interval, counting the condition pulses, counting the timing pulses until a predetermined count of the condition pulses and the timing pulses is reached, and providing the counted timing pulses as part of the pulse train during the time interval.

Claim 33

A method as described in claim 29 in which the step of separating the pulses includes separating the synchronizing pulses from the other pulses in the pulse train.

Claim 34

A method as described in claim 31 in which the separating step further includes controlling switching means to pass the pulses in the pulse train in a different time interval, other than the synchronizing pulse time interval, as a pulse signal.

Claim 35

A method as described in claim 32 in which the providing of each output step includes counting the pulses in a different pulse signal, providing timing pulses, counting the last mentioned timing pulses until a predetermined count of the pulses in the pulse signal and of the last mentioned timing pulses is reached, and providing an output in accordance with the counted last mentioned timing pulses so that the output corresponds to a sensed condition.