Phase shift oscillators using insulated-gate field-effect transistors

Claim 2

The combination comprising: first and second insulated-gate field-effect transistors of first and second conductivity type, respectively, each transistor having a substrate and source and drain regions defining a conduction channel in their respective substrates, and each transistor also having a gate electrode for controlling the conductivity of its channel; first and second terminals for a source of operating potential; an output node connected to the drains of said transistors; an input node connected to the gates of said transistors; relatively low impedance connections between the substrate of said first transistor and said first terminal and the substrate of said second transistor and said second terminal; first substantial direct current impedance means connected between the source electrode of said first transistor and said first terminal and second substantial direct current impedance means connected between the source electrode of said second transistor and said second terminal, for causing the source electrodes of said first and second transistors to be increasingly reversed biased with respect to their substrates with increasing conduction in the source-drain path of said transistors; and approximately an 180* phase-shift feedback network having input and output terminals, said input terminal being connected to said output node, and said output terminal being connected to said input node.

Claim 3

The combination as claimed in claim 1 further including impedance means of substantial value connected between said input and output nodes for establishing the direct current operating level of said transistors.

Claim 4

The combination as claimed in claim 2 wherein said impedance means includes a resistive network connected between said output node and one of said first and second terminals and a biasing resistor connected between the gates of said transistors and a point on said resistive network for applying a greater portion of the operating potential to one than to the other of said first and second transistors.

Claim 5

An oscillator comprising: first and second insulated-gate field-effect transistors of first and second conductivity type, respectively, each transistor having a substrate electrode, source and drain regions defining a conduction channel therebetween; and a gate electrode for controlling the conductivity of its channel; each of said Transistors having a threshold voltage defined as the voltage which it is necessary to apply between the gate and source of the transistor to permit conduction through the conduction channel of the transistor; first and second terminals for a source of operating potential; a network having an input terminal and an output terminal, said network being of the type which phase shifts by approximately 180* signals applied to its input terminal; means connecting the drains of said transistors to said input terminal; means connecting the gates of said transistors to said output terminal; means connecting the substrate of said first transistor to said first terminal; means connecting the substrate of said second transistor to said second terminal; means connecting the source of said first transistor to said first terminal; means connecting the source of said second transistor to said second terminal; and a bias network for establishing the quiescent conduction levels of said transistors comprising a resistive network connected between one of said first and second terminals and the drains of said transistors and a biasing resistor connected at one end to the gates of said transistor and at the other end at a point on said resistive network.

Claim 6

An oscillator comprising: first and second insulated-gate field-effect transistors of first and second conductivity type, respectively, each transistor having a substrate electrode, source and drain regions defining a conduction channel therebetween; and a gate electrode for controlling the conductivity of its channel; each of said Transistors having a threshold voltage defined as the voltage which it is necessary to apply between the gate and source of the transistor to permit conduction through the conduction channel of the transistor; first and second terminals for a source of operating potential; a network having an input terminal and an output terminal, said network being of the type which phase shifts by approximately 180* signals applied to its input terminal; means connecting the drains of said transistors to said input terminal; means connecting the gates of said transistors to said output terminal; means connecting the substrate of said first transistor to said first terminal; means connecting the substrate of said second transistor to said second terminal; means connecting the source of said first transistor to said first terminal; means connecting the source of said second transistor to said second terminal; and a bias network for establishing the quiescent conduction levels of said transistors comprising a resistive network connected between one of said first and second terminals and the drains of said transistors and a biasing resistor connected at one end to the gates of said transistor and at the other end at a point on said resistive network.

Claim 7

The combination as claimed in claim 4 wherein the threshold voltage of one of said transistors is greater than the threshold voltage of the other, and wherein the amplitude of the potential applied between said first and second terminals is less than the sum of the threshold voltages of said transistors.

Claim 8

The combination as claimed in claim 5 wherein that one of the two transistors having the greater threshold voltage is more heavily forward biased than the other.

Claim 9

The combination as claimed in claim 5 wherein said means connecting the source of said first transistor to said first terminal is an impedance of substantially larger value than the impedance of the means connecting the substrate of said transistor to said first terminal and wherein said means connecting the source electrode of said second transistor to said second terminal is an impedance of substantially larger value than the means connecting the substrate of said second transistor to said second terminal.