Communication arrangement allowing network path testing

Claim 2

A communication arrangement for a switching network which comprises a plurality of input terminals, a plurality of output terminals, a plurality of crosspoints defining a plurality of possible paths between said input and output terminals, and means for controlling said crosspoints for selectively establishing paths; said arrangement comprising: a plurality of input circuits each connected to a corresponding one of said input terminals, said input circuits each comprising means responsive to two-valued input signals applied thereto for generating at said corresponding input terminals corresponding current signals of first and second predetermined magnitudes, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three, and a plurality of output circuits each connected to a corresponding one of said output terminals, said output circuits each comprising means for generating data output signals in response to current signals obtained from said connected output terminal exceeding a threshold level of X times said first predetermined magnitude, where (N + 1)/2 < OR = X < N for 1 < N < OR = 2, and (N + 1)/2 < OR = X < 2 for 2 < N < 3 whereby faults, e.g., open circuit conditions, cross to another path, or cross to a foreign potential, can be detected by sequentially applying said two-valued input signals to an input terminal and observing said current signals from an output terminal connected to said input terminal.

Claim 3

A communication arrangement for a switching network which comprises a plurality of input terminals, a plurality of output terminals, a plurality of crosspoints defining a plurality of possible paths between said input and output terminals, and means for controlling said crosspoints for selectively establishing paths; said arrangement comprising: a plurality of input circuits each connected to a corresponding one of said input terminals, said input circuits each comprising a transistor having a base connected to a source of constant voltage, a collector connected directly to said corresponding input terminal, and an emitter connected to ground through a resistance which is varied in magnitude in response to two-valued input signals to establish collector currents of first and second predetermined magnitudes, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three, and a plurality of output circuits each connected to a corresponding one of said output terminals, said output circuits each comprising means for generating data output signals in response to current signals obtained from said connected output terminal exceeding a threshold level of X times said first predetermined magnitude, where (N + 1)/2 < or = X < N for 1 < N < or = 2, and(N + 1)/2 < or = X < 2 for 2 < N < 3 whereby faults, e.g., open circuit conditions, cross to another path, or cross to a foreign potential, can be detected by sequentially applying said two-valued input signals to an input terminal and observing said current signals from an output terminal connected to said input terminal.

Claim 4

A communication arrangement for a switching network which comprises a plurality of input terminals, a plurality of output terminals, a plurality of crosspoints defining a plurality of possible paths between said input and output terminals, and means for controlling said crosspoints for selectively establishing paths; said arrangement comprising: a plurality of input circuits each connected to a corresponding one of said input terminals, said input circuits each comprising a transistor having a base connected to a source of constant voltage, a collector connected directly to said corresponding input terminal, and an emitter connected to ground through a resistance which is varied in magnitude in response to two-valued input signals to establish collector currents of first and second predetermined magnitudes, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three, and a plurality of output circuits each connected to a corresponding one of said output terminals, said output circuits each comprising means for generating data output signals in response to current signals obtained from said connected output terminal exceeding a threshold level of X times said first predetermined magnitude, where (N + 1)/2 < or = X < N for 1 < N < or = 2, and(N + 1)/2 < or = X < 2 for 2 < N < 3 whereby faults, e.g., open circuit conditions, cross to another path, or cross to a foreign potential, can be detected by sequentially applying said two-valued input signals to an input terminal and observing said current signals from an output terminal connected to said input terminal.

Claim 5

A communication arrangement in accordance with claim 2 wherein said resistance comprises at least two resistors in series, and at least one of said resistors is bypassed in response to one value of said two-valued input signals.

Claim 6

A communication arrangement in accordance with claim 3 wherein said bypassing of said resistor shunts, the emitter and collector of a transistor to the base, of which are applied two-valued input signals, only one of said values being of sufficient magnitude to cause saturation.

Claim 7

A communication arrangement in accordance with claim 2 wherein said output circuits each comprise a transistor having a base connected to a source of one constant voltage, a collector connected through a series resistor to a source of another constant voltage, and an emitter connected directly to said corresponding output terminal, and means connected to said transistor for detecting its saturated state.

Claim 8

A communication arrangement in accordance with claim 5 wherein said means for detecting comprises a differential comparator having first and second input terminals connected to the collector and the base of said output circuit transistor respectively.

Claim 9

An arrangement for testing a communication switching network which comprises a plurality of input terminals, a plurality of output terminals, a plurality of crosspoints defining a plurality of possible paths between said input and output terminals, and means for controlling said crosspoints for selectively establishing paths, comprising: a plurality of input circuits each connected to a corresponding input terminal and comprising means responsive to two-valued input signals for applying corresponding current signals of first and second predetermined magnitudes to said corresponding input terminals, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three; a plurality of output circuits each connected to a corresponding output terminal and comprising means for generating data output signals in response to current signals obtained from said connected output terminal exceeding a threshold level of X times said first predetermined magnitude where (N + 1)/2 < or = X < N for 1 < N < or = 2, and (N + 1)/2 < or = X < 2 for 2 < N < 3, and test control means for applying test input signals to any selected one of said input terminals and means for simultaneously observing the resulting data output signals at the output circuit connected through said switching network to said selected input terminal.

Claim 10

An arrangement for testing a communication switching network which comprises a plurality of input terminals, a plurality of output terminals, a plurality of crosspoints defining a plurality of possible paths between said input and output terminals, and means for controlling said crosspoints for selectively establishing paths, comprising: a plurality of input circuits each connected to a corresponding input terminal and comprising means responsive to two-valued input signals for applying corresponding current signals of first and second predetermined magnitudes to said corresponding input terminals, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three; a plurality of output circuits each connected to a corresponding output terminal and comprising means for generating data output signals in response to current signals obtained from said connected output terminal exceeding a threshold level of X times said first predetermined magnitude where (N + 1)/2 < or = X < N for 1 < N < or = 2, and (N + 1)/2 < or = X < 2 for 2 < N < 3, and test control means for applying test input signals to any selected one of said input terminals and means for simultaneously observing the resulting data output signals at the output circuit connected through said switching network to said selected input terminal.

Claim 11

An arrangement for testing a communication switching network which comprises a plurality of input terminals, a plurality of output terminals, a plurality of crosspoints defining a plurality of possible paths between said input and output terminals, and means for controlling said crosspoints for selectively establishing paths, comprising: a plurality of input circuits each connected to a corresponding input terminal and comprising a first transistor having a base connected to a source of constant voltage, a collector connected directly to said corresponding input terminal, and an emitter connected to ground through at least two resistors in series, at least one of said resistors shunting the emitter and collector of a second transistor to the base of which are applied two-valued input signals, only one of said values being of sufficient magnitude to saturate said second transistor, to establish currents of first and second predetermined magnitudes in the collector of said first transistor, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three, a plurality of output circuits each connected to a corresponding output terminal and comprising a transistor having a base connected to a source of one constant voltage, a collector connected through a series resistor to a source of another constant voltage, an emitter connected directly to said corresponding output terminal, and which saturates when the collector current exceeds a threshold level of X times said first predetermined magnitude, where (N + 1)/2 < X < or = N for 1 < N < or = 2, and (N + 1)/2 < X < or = 2 for 2 < N < 3; and a differential comparator haviNg first and second input terminals connected to the collector and base of said transistor, respectively, and test control means for applying test input signals to any selected one of said input terminals and means for simultaneously observing the resulting data output signals at the output circuit connected through said switching network to said selected input terminal.

Claim 12

An arrangement for testing a communication switching network which comprises a plurality of input terminals, a plurality of output terminals, a plurality of crosspoints defining a plurality of possible paths between said input and output terminals, and means for controlling said crosspoints for selectively establishing paths, comprising: a plurality of input circuits each connected to a corresponding input terminal and comprising a first transistor having a base connected to a source of constant voltage, a collector connected directly to said corresponding input terminal, and an emitter connected to ground through at least two resistors in series, at least one of said resistors shunting the emitter and collector of a second transistor to the base of which are applied two-valued input signals, only one of said values being of sufficient magnitude to saturate said second transistor, to establish currents of first and second predetermined magnitudes in the collector of said first transistor, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three, a plurality of output circuits each connected to a corresponding output terminal and comprising a transistor having a base connected to a source of one constant voltage, a collector connected through a series resistor to a source of another constant voltage, an emitter connected directly to said corresponding output terminal, and which saturates when the collector current exceeds a threshold level of X times said first predetermined magnitude, where (N + 1)/2 < X < or = N for 1 < N < or = 2, and (N + 1)/2 < X < or = 2 for 2 < N < 3; and a differential comparator haviNg first and second input terminals connected to the collector and base of said transistor, respectively, and test control means for applying test input signals to any selected one of said input terminals and means for simultaneously observing the resulting data output signals at the output circuit connected through said switching network to said selected input terminal.

Claim 13

In combination: transmitting means responsive to binary input signals applied thereto for generating current signals of first and second predetermined magnitudes to represent the binary states, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three, receiving means for generating output signals responsive to current signals exceeding a threshold level of X times said first predetermined magnitude where (N + 1)/2 < or = X < N for 1 < N < or = 2, and (N + 1)/2 < or = X < 2 for 2 < N < 3, and means for selectively interconnecting one of a plurality of said transmitting means with one of a plurality of said receiving means whereby information may be transmitted from an input terminal to a connected output terminal and circuit faults, e.g., open circuit condition, cross to another circuit path, cross to a foreign potential, associated with a connection between an input terminal and an output terminal can be detected by applying sequences of binary input signals and observing signals at an output connected to said input terminal.

Claim 14

In combination: transmitting means responsive to binary input signals applied thereto for generating current signals of first and second predetermined magnitudes to represent the binary states, said second predetermined magnitude being N times said first predetermined magnitude, N being greater than one and less than three, receiving means for generating output signals responsive to current signals exceeding a threshold level of X times said first predetermined magnitude where (N + 1)/2 < or = X < N for 1 < N < or = 2, and (N + 1)/2 < or = X < 2 for 2 < N < 3, and means for selectively interconnecting one of a plurality of said transmitting means with one of a plurality of said receiving means whereby information may be transmitted from an input terminal to a connected output terminal and circuit faults, e.g., open circuit condition, cross to another circuit path, cross to a foreign potential, associated with a connection between an input terminal and an output terminal can be detected by applying sequences of binary input signals and observing signals at an output connected to said input terminal.

Claim 15

An electrical communications switching network comprising: a plurality of input terminals, a plurality of output terminals, a plurality of semiconductor crosspoint elements defining a plurality of possible transmission paths therethrough, a bias current source associated with each of said input terminals, means for activating the crosspoint elements of a selected path between any selected input terminal and any selected output terminal, the associated current source establishing a bias current of a first predetermined magnitude for the crosspoint elements of said path, input circuit means associated with each of said input terminals and responsive to one value of two-valued input signals applied thereto for increasing said bias current to a second predetermined magnitude N times that of said first predetermined magnitude, N being greater than one and less than three, detection circuit means associated with each of said output terminals comprising a transistor having a collector connected through a resistor to a source of one constant voltage, an emitter connected directly to said output terminal, and a base connected to another source of constant voltage, and which saturates when the collector current exceeds a threshold level of X times said first predetermined magnitude where (N + 1)/2 < or = X < N for 1 < N < or = 2, and (N + 1)/2 < or = X < 2 for 2 < N < 3, and means for detecting the saturated state of said transistor.

Claim 16

An electrical communications switching network comprising: a plurality of input terminals, a plurality of output terminals, a plurality of semiconductor crosspoint elements defining a plurality of possible transmission paths therethrough, a bias current source associated with each of said input terminals, means for activating the crosspoint elements of a selected path between any selected input terminal and any selected output terminal, the associated current source establishing a bias current of a first predetermined magnitude for the crosspoint elements of said path, input circuit means associated with each of said input terminals and responsive to one value of two-valued input signals applied thereto for increasing said bias current to a second predetermined magnitude N times that of said first predetermined magnitude, N being greater than one and less than three, detection circuit means associated with each of said output terminals comprising a transistor having a collector connected through a resistor to a source of one constant voltage, an emitter connected directly to said output terminal, and a base connected to another source of constant voltage, and which saturates when the collector current exceeds a threshold level of X times said first predetermined magnitude where (N + 1)/2 < or = X < N for 1 < N < or = 2, and (N + 1)/2 < or = X < 2 for 2 < N < 3, and means for detecting the saturated state of said transistor.