Synchronization network for pcm multiplexing systems

Claim 1

A time-sharing system for the transmission of several incoming messages in interleaved relationship over an outgoing signal path, comprising: a plurality of memory sections each including a register with a multiplicity of stages for the temporary storage of elemental units of a respective incoming message; a source of clock pulses for each memory section; distributing means in each memory section responsive to said clock pulses for enabling the stages of said register in cyclic succession to store incoming elemental message units for overlapping periods of k clock pulses, k being the number of said stages; a source of reading pulses common to all said memory sections, said reading pulses having a cadence substantially higher than that of said clock pulses and being delivered to each memory section during recurring scanning cycles at a rate of k reading pulses per cycle, the length of a scanning cycle being approximately equal to that of a storage period of any of said memory sections; multiplexing means controlled by said reading pulses for sampling the contents of respective register stages of each memory section, one stage at a time, during k consecutive subcycles of any scanning cycle and for transmitting said contents in the order of their sampling over said outgoing signal path, said multiplexing means including a set of k normally blocked readout gates for said stages and a cyclic counter with a counting capacity k for said reading pulses adapted to unblock said gates in a predetermined sequence; a first signal generator in each memory section controlled by said clock pulses for producing a succession of timing signals substantially coextensive with alternate storage periods of one stage; a second signal generator in each memory section controlled by said counter for producing, in the presence of a predetermined count, a monitoring signal lasting substantially less than a scanning cycle and bracketing the reading pulse which unblocks the readout gate of said one stage, said monitoring signal normally occurring once every two scanning cycles; and logical circuitry connected to said generator for detecting a coincidence of said monitoring signal with a timing signal and, upon such coincidence, transmitting to said counter a corrective signal modifying the count thereof to an extent shifting said monitoring signal to an interval between successive timing signals.