Fabrication of integrated microcircuits utilizing dielectric p-n-junction isolation

Abstract

Abstract A SEMICONDUCTOR DEVICE FOR INTEGRATED MICROCIRCUITS HAVING A NUMBER OF FUNCTIONAL ELEMENTS, INCLUDES A SEMICONDUCTOR SUBSTREAM, A DIELECTRIC INSULATION LAYER DISPOSED ON THE SUBSTRATUM, LOW-OHMIC HIGHLY DOPED SEMICONDUCTIVE LAYERS LOCATED IN THE REGIONS OF RESPECTIVE FUNCTIONAL ELEMENTS. A DIELECTRIC INSULATION LAYER COATS THE BOTTOM AND SIDE SURFACES OF THE LOW-OHMIC LAYERS, WITH THE THICKNESS OF THE DIELECTRIC INSULATION LAYER BEING GREATER IN THE REGIONS BETWEEN THE LOQ-OHMIC LAYER. SEMICONDUCTIVE BODY LAYERS ADJOIN THE OPEN UPPER SURFACE OF THE LOW-OHMIC LAYERS AND OVERLAP THE OPEN UPPER SURFACE OF TOP SURFACE OF THE SIDE PORTIONS OF THE DIELECTRIC INSULATION LAYER. THE SEMICONDUCTIVE BODY LAYERS HAVE THE SAME TYPE OF CONDUCTIVITY AS THE LOW-OHMIC LAYERS. P-N JUNCTIONS DISPOSED ON THE DIELECTRIC INSULATION LAYER FORM LATERAL INSULATION FRAMES AROUND RESPECTIVE SEMICONDUCTIVE BODY LAYERS. THIRD INSULATING LAYERS ARE PROVIDED ON THE UPPER SURFACE OF RESPECTIVE FUNCTIONAL ELEMENTS.

Inventors

• 👤 M Roder

Bibliographic Details