Digital phase tracker

Claim 2

Means for maintaining a fIrst signal phase locked to a second signal, said first and second signals having first and second predetermined points respectively, comprising: a source of clock pulses; a digital counter counting said clock pulses for generating said first signal; gate means enabled by one of said predetermined points and disabled by the other of said predetermined points for generating an output signal when enabled; second means for counting the number of times said gate means is enabled; third means for counting clock pulses applied thereto; means responsive to said output signal for applying said clock pulses to said third means; means for obtaining the quotient of the count contained in said third means by the count contained in said second means whereby the average number of clock pulses occurring between one said predetermined point and the other said predetermined point is obtained; and, means for blocking clock pulses from being counted by said digital counter in response to said average number of clock pulses.

Claim 3

Means for maintaining a first signal in phase lock with a second signal, wherein said first and second signals are at the same frequency, comprising: means for generating clock pulses at a pulse repetition frequency which is a whole integer (n) multiple of said same frequency; gate means enabled by a predetermined point on one of said first or second signals and disabled by a predetermined point on the other of said first or second signals; a first divide-by-n counter means for counting the number of enable-disable cycles of said gate means and for generating a first output signal upon counting n cycles; a second divide-by-n2 counter means for counting the number of clock pulses occurring during n cycles of said gate means while said gate means is enabled, and for generating a second output signal when a predetermined number of clock pulses have been counted; memory means for storing and generating said first signal; and, logic means for determining the number of clock pulses generated between said first output signal and said second output signal and for varying the phase of said first signal in accordance with the number of clock pulses so determined.

Claim 4

Means for maintaining a first signal in phase lock with a second signal, wherein said first and second signals are at the same frequency, comprising: means for generating clock pulses at a pulse repetition frequency which is a whole integer (n) multiple of said same frequency; gate means enabled by a predetermined point on one of said first or second signals and disabled by a predetermined point on the other of said first or second signals; a first divide-by-n counter means for counting the number of enable-disable cycles of said gate means and for generating a first output signal upon counting n cycles; a second divide-by-n2 counter means for counting the number of clock pulses occurring during n cycles of said gate means while said gate means is enabled, and for generating a second output signal when a predetermined number of clock pulses have been counted; memory means for storing and generating said first signal; and, logic means for determining the number of clock pulses generated between said first output signal and said second output signal and for varying the phase of said first signal in accordance with the number of clock pulses so determined.

Claim 5

Means as recited in claim 2 wherein said memory means comprises a third divide-by-n counter which is counted down by said clock pulses applied thereto to generate said first signal.

Claim 6

Means as recited in claim 3 wherein said logic means includes means for applying said clock pulses to said memory means, said applying means being inhibited in response to said determined number of clock pulses whereby the phase of said first signal is varied.

Claim 7

Means as recited in claim 3 wherein all said recited counters are digital counters.

Claim 8

Means as recited in claim 5 whereIn said digital counters each consist of a plurality of flip-flop stages.

Claim 9

Means as recited in claim 5 wherein said second counter includes two divide-by-n counters serially connected whereby the second of said counters counts the number of times the first of said counters counts n clock pulses.

Claim 10

Means as recited in claim 7 wherein the second of said counters generates said second output signal when it attains a predetermined count.

Claim 11

Means as recited in claim 8 wherein said predetermined count is the number of clock pulses generated between said predetermined points on said first and second signals when said first and second signal are in phase lock.

Claim 12

Means as recited in claim 2 wherein said logic means comprises means for determining which of said fIrst and second output signals occurs first and the number of clock pulses generated between said first generated of said first and second output signals and the second generated of said first and second output signals, and for varying the phase of said first signal in accordance with the number of clock pulses so determined and in a direction related to which of said first and second output signals occurred first.

Claim 13

Means for maintaining a memorized signal in phase lock with an input signal, wherein said memorized and input signals are at the same frequency, comprising: a source of clock pulses at a pulse repetition freQuency which is a whole integer (n) multiple of said same frequency; memory means responsive to said clock pulses for generating said memorized signal; gate means enabled by a first predetermined point on one of said memorized or input signals and disabled by a second predetermined point on the other of said memorized or input signals for generating a gate output signal while enabled; a first divide-by-n counter means for counting the number of gate output signals generated and for generating a first output signal upon counting n gate output signals; a second divide-by-n2 counter means for counting the total number of clock pulses, in groups of n clock pulses each, which are generated while said gate means is enabled, and for generating a second output signal upon attaining a predetermined count; means for determining the number of clock pulses occurring between said first and second output signals, regardless of which occurs fIrst; and, means for varying the phase of the signal stored and generated by said memory means in a first direction when one of said first and second output Signals occurs first and for varying the phase of the signal stored and generated by said memory means in the other direction when the other of said first and second output signals occurs first.

Claim 14

Means for maintaining a memorized signal in phase lock with an input signal, wherein said memorized and input signals are at the same frequency, comprising: a source of clock pulses at a pulse repetition freQuency which is a whole integer (n) multiple of said same frequency; memory means responsive to said clock pulses for generating said memorized signal; gate means enabled by a first predetermined point on one of said memorized or input signals and disabled by a second predetermined point on the other of said memorized or input signals for generating a gate output signal while enabled; a first divide-by-n counter means for counting the number of gate output signals generated and for generating a first output signal upon counting n gate output signals; a second divide-by-n2 counter means for counting the total number of clock pulses, in groups of n clock pulses each, which are generated while said gate means is enabled, and for generating a second output signal upon attaining a predetermined count; means for determining the number of clock pulses occurring between said first and second output signals, regardless of which occurs fIrst; and, means for varying the phase of the signal stored and generated by said memory means in a first direction when one of said first and second output Signals occurs first and for varying the phase of the signal stored and generated by said memory means in the other direction when the other of said first and second output signals occurs first.

Claim 15

Means as recited in claim 11 wherein said second counter means comprises third and fourth divide-by-n counters, said third counter counting the total number of clock pulses occurring while said gate means is enabled and said fourth counter counting the number of times said third counter fills.

Claim 16

Means as recited in claim 12 wherein phase lock of said memorized and input signals occurs when said gate means is enabled just long enough during an average length enabled period to permit n/2 clock pulses to be counted by said second counter means, said second output signal being generated when said fourth counter has attained an n/2 count.