Frequency multiplying circuit utilizing time gates and switching signals of differing phases

Claim 2

A multiplying circuit including in combination: A first time gate having an input and first and second outputs and responsive to an alternating switching signal for coupling the input alternately with the first and second outputs on alternate halfcycles of the switching signal; means for supplying an input signal to the input of said first time gate; means for supplying a first alternating switching signal at a predetermined frequency to said first time gate; second and third time gates, each having an input connected to a different output of said first time gate and each having first and second outputs, said second and third time gates each being responsive to an alternating switching signal applied thereto for coupling the inputs thereof alternately with the first and second outputs thereof on alternate half-cycles of the switching signal; means for supplying a second switching signal at the predetermined frequency of the first switching signal, but at a different phase, to said second and third time gates; means for combining the first output of the second time gate with the second output of the third time gate; and means for combining the second output of the second time gate with the first output of the third time gate.

Claim 3

The combination according to claim 1 wherein said means for applying the second switching signal to said second and third time gates includes phase-shift circuit means responsive to the output of said means for applying the first switching signal to said first time gate.

Claim 4

A signal multiplying circuit including in combination: a first time gate having an input and first and second outputs; means for supplying an input signal to the input of the first time gate; means for supplying a first switching signal at a predetermined frequency to the first time gate for switching the input signal applied to the input thereof from the first output to the second output on alternate half-cycles of the switching signal; second and third time gates, the inputs of which constitute, respectively, the first and second outputs of the first time gate, each of the second and third time gates having first and second outputs; means for applying a second switching signal at said predetermined frequency and in phase quadrature with the first switching signal to the second and third time gates for causing the second and third time gates to alternately switch the signals applied to the inputs thereof to the first and second outputs thereof on alternate half-cycles of the switching signal applied thereto; and means for combining predetermined outputs of the second and third time gates to develop an output signal.

Claim 5

A signal multiplying circuit including in combination: a first time gate having an input and first and second outputs; means for supplying an input signal to the input of the first time gate; means for supplying a first switching signal at a predetermined frequency to the first time gate for switching the input signal applied to the input thereof from the first output to the second output on alternate half-cycles of the switching signal; second and third time gates, the inputs of which constitute, respectively, the first and second outputs of the first time gate, each of the second and third time gates having first and second outputs; means for applying a second switching signal at said predetermined frequency and in phase quadrature with the first switching signal to the second and third time gates for causing the second and third time gates to alternately switch the signals applied to the inputs thereof to the first and second outputs thereof on alternate half-cycles of the switching signal applied thereto; and means for combining predetermined outputs of the second and third time gates to develop an output signal.

Claim 6

The combination according to claim 3 wherein the second switching signal applied to the second and third time gates is obtained from the output of a phase shifting means having as its input the switching signal applied to the first time gate, with the phase shifting means providing a 90* phase shift to signals applied to the input thereof.

Claim 7

The combination according to claim 3 wherein said signal multiplying circuit is for use in a receiver for receiving a composite stereophonic multiplex radio signal comprising a carrier FM modulated by an audio frequency summation signal, a difference signal of the same information amplitude modulated on a suppressed subcarrier, and a continuous wave pilot signal subharmonically related to said subcarrier signal; the means for supplying an input signal to the input of the first time gate supplies at least the subcarrier component of said composite signal to such input; the means for supplying the first switching signal is responsive to the pilot signal portion of the composite signal, with said predetermined frequency being the frequency of the pilot signal portion; and the means for combining predetermined outputs of the second and third time gates includes first combining means for combining one of the outputs of each of the second and third time gates to develop one of said audio signals substantially separated from the other of said audio signals, and second combining means for combining the other of the outputs of each of the second and third time gates to develop the other of said audio signals substantially separated from the one of said audio signals.

Claim 8

The combination according to claim 5 wherein the second switching signal is obtained from the output of a phase shifting means having as its input the first switching signal, with the phase shifting means providing a 90* phase-shift to signals applied to the input thereof.

Claim 9

The combination according to claim 5 wherein the first combining means combines the first output of the second time gate and the second output of the third time gate, the second combining means combines the second output of the second time gate and the first output of the third time gate, and the means for applying the second switching signal to the second and third time gates to alternately enable the first outputs and the second outputs thereof to pass signals applied to the inputs thereof.

Claim 10

The combination according to claim 7 wherein the input signal supplying means supplies at least the summation signal and the modulated suppressed carrier to the first gating means and includes an input transistor; and wherein the first, second and third time gates each include first and second switching transistors, all of said transistors having a base, emitter, and collector, the input signals being supplied to the base of the input transistor, the collector of which is coupled with the emitters of the transistors of the first time gate; the first and second switching signals are supplied to the bases of the transistors of the respective first, second and third time gates, with the first and second transistors thereof conducting on alternate half-cycles of the supplied switching signals; the collectors of the first and second transistors of the time gates comprise the first and second outputs thereof, respectively, and the emitters of the transistors in each time gate are interconnected to form the input thereof.

Claim 11

The combination according to claim 7 wherein the means for applying the second switching signal includes means for shifting the phase of the first switching signal, with the output of the phase shifting means constituting the second switching signal.

Claim 12

The combination according to claim 9 wherein the phase shifting means shifts the phase of the first switching signal 90* to provide the second switching signal.