One-bit data transmission system

Claim 2

In a signal transmission system comprising: a plurality of groups of distributed one-bit data sources, each data source providing a first signal when in a normal first state, for providing a second signal when in an abnormal second state, each of said data sources in a group having a priority with respect to the data sources in other groups; a control center, for receiving the address of a data source which is in an abnormal second state ; a plurality of stations, connected to said control center via transmission lines including address and data lines and also being connected to said data sources, for forwarding said second signals to said control center from said data sources over said data line and for coupling, from said control center to said sources, address signals via said address lines; the method of communicating between said control center and said data sources, comprising the steps of: transmitting, from said control center to said dats sources, a first address signal having at least a clock portion made up of a plurality of bits together with a start pulse and an end pulse immediately before and after said clock bits respectively, the bit positions of said bits in said clock portion corresponding to respective groups of data sources; transmitting over said data line , from each group of data sources to said control center, a group data signal representative of the states of said data sources in each said group, each group data signal being synchronized with the respective bit portion of said clock portion of said first address signal, said states corresponding to one of said first and second signals provided by said data sources ; transmitting, from said control center to a group of data sources, a second address signal comprising a plurality of bits representing an address of one group including at least one data source in an abnormal state and a plurality of bits representing a clock portion, the bit positions of said clock portion corresponding to the respective data sources in said group; and transmitting, from said data sources in said group to said control center, a second data signal representative of one of said first and second signals provided by each data source in said group, said second data signal being synchronized with each bit of said clock portion in said second address signal.

Claim 3

In a signal transmission system comprising: a plurality of groups of distributed one-bit data sources, each data source providing a first signal when in a normal first state, for providing a second signal when in an abnormal second state, each of said data sources in a group having a priority with respect to the data sources in other groups; a control center, for receiving the address of a data source which is in an abnormal second state ; a plurality of stations, connected to said control center via transmission lines including address and data lines and also being connected to said data sources, for forwarding said second signals to said control center from said data sources over said data line and for coupling, from said control center to said sources, address signals via said address lines; the method of communicating between said control center and said data sources, comprising the steps of: transmitting, from said control center to said dats sources, a first address signal having at least a clock portion made up of a plurality of bits together with a start pulse and an end pulse immediately before and after said clock bits respectively, the bit positions of said bits in said clock portion corresponding to respective groups of data sources; transmitting over said data line , from each group of data sources to said control center, a group data signal representative of the states of said data sources in each said group, each group data signal being synchronized with the respective bit portion of said clock portion of said first address signal, said states corresponding to one of said first and second signals provided by said data sources ; transmitting, from said control center to a group of data sources, a second address signal comprising a plurality of bits representing an address of one group including at least one data source in an abnormal state and a plurality of bits representing a clock portion, the bit positions of said clock portion corresponding to the respective data sources in said group; and transmitting, from said data sources in said group to said control center, a second data signal representative of one of said first and second signals provided by each data source in said group, said second data signal being synchronized with each bit of said clock portion in said second address signal.

Claim 4

In a signal transmission system comprising: a plurality of groups of distributed one-bit data sources, each data source providing a first signal when in a normal first state, for providing a second signal when in an abnormal second state, each of said data sources in a group having a priority with respect to the data sources in other groups; a control center, for receiving the address of a data source which is in an abnormal second state ; a plurality of stations, connected to said control center via transmission lines including address and data lines and also being connected to said data sources, for forwarding said second signals to said control center from said data sources over said data line and for coupling, from said control center to said sources, address signals via said address lines; the method of communicating between said control center and said data sources, comprising the steps of: transmitting, from said control center to said dats sources, a first address signal having at least a clock portion made up of a plurality of bits together with a start pulse and an end pulse immediately before and after said clock bits respectively, the bit positions of said bits in said clock portion corresponding to respective groups of data sources; transmitting over said data line , from each group of data sources to said control center, a group data signal representative of the states of said data sources in each said group, each group data signal being synchronized with the respective bit portion of said clock portion of said first address signal, said states corresponding to one of said first and second signals provided by said data sources ; transmitting, from said control center to a group of data sources, a second address signal comprising a plurality of bits representing an address of one group including at least one data source in an abnormal state and a plurality of bits representing a clock portion, the bit positions of said clock portion corresponding to the respective data sources in said group; and transmitting, from said data sources in said group to said control center, a second data signal representative of one of said first and second signals provided by each data source in said group, said second data signal being synchronized with each bit of said clock portion in said second address signal.

Claim 5

A signal transmission system according to claim 1, wherein the method of communicating between said control center and said data sources further comprises step of decoding, at said control center, said group data signal, in accordance with the bit positions of said group data signal, to detect the data source group having the highest priority level among those groups providing at least one second signal from said data sources, so that in the third mentioned transmitting step, said second address signal, representing said group of the highest priority level, can be transmitted from said control center to the data sources.

Claim 6

In a signal transmission system including: a plurality of groups of interrupt signal sources, each of which provides one-bit data represented by a first signal corresponding to a normal first state of a signal source and a second signal corresponding to an abnormal second State of a signal source, said groups being distributed according to priority levels of interrupt requests; a plurality of controlled signal sources, distributed in a process field, from which sensor signals corresponding to process variables are generated; a control center for detecting the address of a signal source requesting an interrupt from among said interrupt signal sources, performing system control functions, processing sensor signals and transmitting the necessary manipulative signals to said control signal sources for executing process functions; a plurality of stations coupled to said control center, said interrupt signal sources and said controlled signal sources; and a transmission line having an address line and a data line connected between said stations and said control center; the method of communicating between said control center and said sources, so as to ensure interruption of said system operation in the event of a malfunction during the process in which said controlled signal sources are utilized, comprising the steps of: transmitting, from said control center over said address line to said stations, a first address signal having a plurality of bits making up an address field representative of the address of one controlled signal source and a plurality of bits making up an clock field ; transmitting, from a station over said data line to said control center, a first interrupt data signal representative of a group of interrupt signal sources having a specified priority level, said interrupt data signal being synchronized with the bit positions of said address field; transmitting a sensor signal from said controlled signal source over said data line to said control center and a manipulative signal from the control center over said data line to said controlled signal source, said sensor signal and manipulated signal being synchronized with the bit positions of said clock field; transmitting, from said control center over said address line to the group of interrupt signal sources requesting an interrupt, a second address signal comprising an address field made up of a first plurality of bits and a clock field made up of a second plurality of bits, the bits of said clock field corresponding to the respective one-bit data sources of said group of interrupt signal sources; and transmitting, from said requesting group over said data line to said control center, a second interrupt data signal representative of each data source in said group providing said second signals, said second interrupt signal being synchronized with said clock field in said second address signal.

Claim 7

In a signal transmission system including: a plurality of groups of interrupt signal sources, each of which provides one-bit data represented by a first signal corresponding to a normal first state of a signal source and a second signal corresponding to an abnormal second State of a signal source, said groups being distributed according to priority levels of interrupt requests; a plurality of controlled signal sources, distributed in a process field, from which sensor signals corresponding to process variables are generated; a control center for detecting the address of a signal source requesting an interrupt from among said interrupt signal sources, performing system control functions, processing sensor signals and transmitting the necessary manipulative signals to said control signal sources for executing process functions; a plurality of stations coupled to said control center, said interrupt signal sources and said controlled signal sources; and a transmission line having an address line and a data line connected between said stations and said control center; the method of communicating between said control center and said sources, so as to ensure interruption of said system operation in the event of a malfunction during the process in which said controlled signal sources are utilized, comprising the steps of: transmitting, from said control center over said address line to said stations, a first address signal having a plurality of bits making up an address field representative of the address of one controlled signal source and a plurality of bits making up an clock field ; transmitting, from a station over said data line to said control center, a first interrupt data signal representative of a group of interrupt signal sources having a specified priority level, said interrupt data signal being synchronized with the bit positions of said address field; transmitting a sensor signal from said controlled signal source over said data line to said control center and a manipulative signal from the control center over said data line to said controlled signal source, said sensor signal and manipulated signal being synchronized with the bit positions of said clock field; transmitting, from said control center over said address line to the group of interrupt signal sources requesting an interrupt, a second address signal comprising an address field made up of a first plurality of bits and a clock field made up of a second plurality of bits, the bits of said clock field corresponding to the respective one-bit data sources of said group of interrupt signal sources; and transmitting, from said requesting group over said data line to said control center, a second interrupt data signal representative of each data source in said group providing said second signals, said second interrupt signal being synchronized with said clock field in said second address signal.

Claim 8

A signal transmission system according to claim 3, wherein the method of communicating between said control center and said interrupt signal sources further comprises step of decoding, at said control center, said first interrupt data signal in accordance with the bit positions of said first interrupt data signal to detect the interrupt signal source group having the highest priority level among those groups providing at least one second signal from said interrupt sources, so that, in the fourth mentioned transmitting step, said second address signal representing said group of the highest priority level can be transmitted from the control center to the interrupt signal sources.

Claim 9

A signal transmission system comprising: a plurality of groups of interrupt signal sources, each of which provides one-bit data represented by a first signal corresponding to a normal first state of a signal source and a second signal corresponding to an abnormal second state of a signal source, said groups being distributed according to priority levels of interrupt requests; a plurality of controlled signal sources, distributed in a process field, from which sensor signals corresponding to process variables are generated; a control center for detecting the address of a signal source requesting an interrupt from among said interrupt signal sources, performing system control functions, processing sensor signals and transmitting the necessary manipulative signals to said controlled sources for executing process functions; a plurality of stations coupled to said control center, said interrupt signal sources and said controlled signal sources; a transmission line having an address line and a data line connected between said stations and said control center; and means for transmitting address and data signals between said control center and said stations over said respective address lines and data lines ; wherein said control center includes means for generating a first address signal having a first plurality of bits making up an address field representative of the address of a controlled signal source associated therewith and a second plurality of bits making up a clock field; each of said stations includes means, responsive to said first address signal, for generating a first interrupt data signal, representative of a group of interrupt signal sources having a specified priority level, said interrupt data signal having a third plurality of bits corresponding to the groups of data sources providing said second signals and being synchronized with said first plurality of bits in the address field of said first address signal; said control center further includes means, responsive to said first interrupt data signal transmitted thereto over said transmission line, for generating a second address signal comprising an address field made up of a fourth plurality of bits and a clock field made up of a fifth plurality of bits, the bit positions of said fifth plurality of bits corresponding to said one-bit data sources in said groups of said interrupt signal sources; and said stations also include means, responsive to said second address signal, for generating a second data signal having a sixth plurality of bits, each of which is representative of a respective data source of said plurality of data sources within said group, said second data signal having each bit positioned synchronized with a respective bit position within the clock field of said second address signal.

Claim 10

A signal transmission system comprising: a plurality of groups of interrupt signal sources, each of which provides one-bit data represented by a first signal corresponding to a normal first state of a signal source and a second signal corresponding to an abnormal second state of a signal source, said groups being distributed according to priority levels of interrupt requests; a plurality of controlled signal sources, distributed in a process field, from which sensor signals corresponding to process variables are generated; a control center for detecting the address of a signal source requesting an interrupt from among said interrupt signal sources, performing system control functions, processing sensor signals and transmitting the necessary manipulative signals to said controlled sources for executing process functions; a plurality of stations coupled to said control center, said interrupt signal sources and said controlled signal sources; a transmission line having an address line and a data line connected between said stations and said control center; and means for transmitting address and data signals between said control center and said stations over said respective address lines and data lines ; wherein said control center includes means for generating a first address signal having a first plurality of bits making up an address field representative of the address of a controlled signal source associated therewith and a second plurality of bits making up a clock field; each of said stations includes means, responsive to said first address signal, for generating a first interrupt data signal, representative of a group of interrupt signal sources having a specified priority level, said interrupt data signal having a third plurality of bits corresponding to the groups of data sources providing said second signals and being synchronized with said first plurality of bits in the address field of said first address signal; said control center further includes means, responsive to said first interrupt data signal transmitted thereto over said transmission line, for generating a second address signal comprising an address field made up of a fourth plurality of bits and a clock field made up of a fifth plurality of bits, the bit positions of said fifth plurality of bits corresponding to said one-bit data sources in said groups of said interrupt signal sources; and said stations also include means, responsive to said second address signal, for generating a second data signal having a sixth plurality of bits, each of which is representative of a respective data source of said plurality of data sources within said group, said second data signal having each bit positioned synchronized with a respective bit position within the clock field of said second address signal.

Claim 11

A system according to claim 5, wherein said control center comprises a central processing unit, a central input unit coupled therewith for receiving data signals from said stations, and a central output unit for transmitting said address signals to said stations.

Claim 12

A system according to claim 6, wherein each station includes an address signal output unit, coupled to said address line, for receiving said address signals, an address decoder connected to the output of said address signal output unit for decoding said address signals into respective interrupt and controlled signal source access signals, and a data signal output unit and a data signal input unit coupled to said data line and said sources for transferring data therebetween.

Claim 13

A system according to claim 7, wherein each of said stations further includes a source control unit coupled between said address decoder , said data signal input and output units and said sources , for transferring data and address signals therebetween.

Claim 14

A system according to claim 7, wherein said address decoder comprises a clock generator circuit, coupled to said address signal output unit, for generating a plurality of clock field bits from said address signal bits in said address signal, a recognizing circuit, coupled to said address signal output unit, for identifying the beginning and termination of address field bits and for providing an output signal representative thereof, a discriminating circuit, responsive to the output of said address signal output unit for generating a signal representative of the duration of an address field, and a decoding circuit, responsive to the output of said address signal output unit, for enabling said control unit for the duration of a clock field signal.

Claim 15

A system in accordance with claim 9, wherein each of said stations further includes a source control unIt coupled between said address decoder, said data signal input and output units and said sources for transferring data and address signals therebetween.

Claim 16

A system according to claim 10, wherein said source control unit comprises respective control circuits each connected to a number of interrupt data sources and controlled signal sources and responsive to the outputs of each of the circuits in said address decoder for accessing said sources in dependence upon the address thereof as decoded by said address decoder, and a control unit output gating circuit responsive to the output of each of said respective control circuits for transferring said first and second data signals provided by said one-bit sources to said signal output unit for transmission over said data line to said central input unit of said control center.

Claim 17

A system in accordance with claim 11, wherein the output of said data signal input unit is coupled only to the one of said control unit control circuits for accessing said controlled signal sources.

Claim 18

A system according to claim 11, wherein the control unit control circuit for accessing said one-bit data interrupt signal sources comprises: a first plurality of interrupt generating status preserving circuits respectively coupled to the outputs of each of said interrupt sources, first and second pluralities of AND gates, one input of each of said first and second pluralities being connected to the output of a respective interrupt generating status preserving circuit, the output of each of said AND gates being connected to an output OR circuit; a counter-decoder circuit, responsive to the outputs of said clock generator circuit, said recognizing circuit and said discriminating circuit, for providing a plurality of pulse position outputs corresponding to the bit positions in said address and clock fields in an address signal, the outputs corresponding to the address bit field positions being connected to respective ones of said first plurality of AND gates, said outputs corresponding to clock field bit positions being connected to respective inputs of said plurality of AND gates, and wherein each of said second plurality of AND gates is connected to a corresponding priority level output of said decoding circuit.

Claim 19

A system in accordance with claim 6, wherein said central input unit comprises a data input unit and an address input unit, coupled to said transmission lines and to said central processing unit, and a recognizing unit coupled to said data input unit, said processing unit and having its output connected to said central output unit.

Claim 20

A system according to claim 14, wherein said central output unit comprises a clock generator, an address memory unit and a pair of transmitters for address and data signals, responsive to said processing unit and said clock generator for transmitting address and process control data signals to said station.

Claim 21

A system according to claim 14, wherein said address input unit comprises an address receiver circuit connected to said address line, a clock producing circuit, a pulse producing circuit and a discriminating circuit, connected to the output of said address receiver circuit, and being coupled to a bit position recognizing unit, for decoding the address of a signal source providing interrupt signals.

Claim 22

A system according to claim 16, wherein said data input unit comprises a data receiver circuit coupled to said data line, a shift register connected thereto and to said bit position recognizing unit of said address signal input unit, a holding register logically coupled to the output of said shift register for transferring the output thereof to said processing unit.

Claim 23

A system according to claim 17, wherein each station includes an address signal output unit coupled to said address line for receiving said address signals, an address decoder connected to the output of said address signal output unit for decoding said address signals into respective interrupt and Controlled signal source access signals, and a data signal output unit and a data signal input unit coupled to said data line and said sources for transferring data therebetween.

Claim 24

A system in accordance with claim 18, wherein said address decoder comprises a clock generator circuit, coupled to said address signal output circuit, for generating a plurality of clock field bits from said address signal bits in said address signal, a recognizing circuit, coupled to said address signal output unit for identifying the beginning and termination of address field bits and for providing an output signal representative thereof, a discriminating circuit, responsive to the outputs of said address signal output unit for generating a signal representative of the duration of an address field and a decoding circuit, responsive to the output of said address signal output unit for enabling said control unit for the duration of a clock field signal.

Claim 25

A system according to claim 19, wherein each of said stations further includes a source control unit coupled between said address decoder, said data signal input and output units and said sources for transferring the data and address signals therebetween.

Claim 26

A system in accordance with claim 20, wherein said source control unit comprises respective control circuits, each connected to a number of interrupt data sources and controlled signal sources and responsive to the outputs of each of the circuits in said address decoder for accessing said sources in dependence upon the address thereof as decoded by said address decoder, and a control unit output gating circuit responsive to the outputs of each of said respective control circuits for transferring said first and second data signals provided by said one-bit sources to said signal output unit for transmission of said data line to said central input unit of said control center.