Patent US3718903A successfully refreshed from Google Patents.
US3718903A
Expired / Lapsed
US
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Circuit arrangement for checking stored information
Assignee: Fujitsu Ltd
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Filing: 1970-11-18
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Granted: 1973-02-27
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Expires: 1990-11-18
Abstract
Abstract A counter counts specific bits in each of the digits of information and indicates specific bits to form check bits. An input supplies stored information of N digits each including a determined number of bits to the inputs of the counter. A first shift register has inputs coupled to the outputs of the counter for determining a first check digit by counting the supplied information and storing the output of the counter. A write circuit is connected to an output of the first shift register and is positioned in operative proximity with a magnetic storage for recording the first check digit in the magnetic storage. A readout circuit is connected to an input of the first shift register and is positioned in operative proximity with the magnetic storage for reading out information from the magnetic storage. A second shift register has an input coupled to the input and outputs coupled to the inputs of the first shift register for determining a second check digit by counting determined digits of the supplied information and transferring the counted determined digits to the first register. The write circuit records the second check digit in the magnetic storage. A collator has inputs coupled to the input and to the outputs of the counter and of the first shift register for collating the first check digit in the output of the counter with the first check digit read out from the magnetic storage and for collating the second check digit in the output of the second shift register with the second check digit read out from the magnetic storage. A feedback coupled between the outputs of the first shift register and the input adds parity bits to the stored information. An output connected to the feedback provides the stored information with the included parity bits.
Inventors
- 👤 M Oiso
- 👤 Y Endo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:48
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
351 words
Circuit arrangement for checking stored information comprising counter means for determining a first check digit by counting specific bits in each of the information, said counter means having inputs and outputs; input means for supplying stored information of N digits each including a determined number of bits to the inputs of Said counter means; a plurality of AND gates; first shift register means having two types of outputs and two types of inputs, one of the two types of inputs being coupled through said AND gates to the outputs of said counter means for storing the first check digit; magnetic storage means; write means connected to one of the two types of outputs of said first shift register means and positioned in operative proximity with said magnetic storage means for recording data including said first check digit in said magnetic storage means; readout means connected to the other of the two types of inputs of said first shift register means and positioned in operative proximity with said magnetic storage means for reading out information from said magnetic storage means; an additional plurality of AND gates; second shift register means having an input coupled to said input means and outputs coupled to the one of the two types of inputs of said first shift register means through said additional AND gates for determining a second check digit by counting determined digits of the supplied information and transferring the counted determined digits to said first shift register means; collating means having an output and inputs coupled to the outputs of said counter means, of said second shift register means and of said first shift register means for collating the first check digit in the output of said counter means with the first check digit read out from said magnetic storage means and for collating the second check digit in the output of said second shift register with the second check digit read out from said magnetic storage means; and feedback means coupled between the outputs of said first shift register means and said input means for adding parity bits to said stored information.
Claim 2
Dependent Claim
351 words
Circuit arrangement for checking stored information comprising counter means for determining a first check digit by counting specific bits in each of the information, said counter means having inputs and outputs; input means for supplying stored information of N digits each including a determined number of bits to the inputs of Said counter means; a plurality of AND gates; first shift register means having two types of outputs and two types of inputs, one of the two types of inputs being coupled through said AND gates to the outputs of said counter means for storing the first check digit; magnetic storage means; write means connected to one of the two types of outputs of said first shift register means and positioned in operative proximity with said magnetic storage means for recording data including said first check digit in said magnetic storage means; readout means connected to the other of the two types of inputs of said first shift register means and positioned in operative proximity with said magnetic storage means for reading out information from said magnetic storage means; an additional plurality of AND gates; second shift register means having an input coupled to said input means and outputs coupled to the one of the two types of inputs of said first shift register means through said additional AND gates for determining a second check digit by counting determined digits of the supplied information and transferring the counted determined digits to said first shift register means; collating means having an output and inputs coupled to the outputs of said counter means, of said second shift register means and of said first shift register means for collating the first check digit in the output of said counter means with the first check digit read out from said magnetic storage means and for collating the second check digit in the output of said second shift register with the second check digit read out from said magnetic storage means; and feedback means coupled between the outputs of said first shift register means and said input means for adding parity bits to said stored information.
Claim 3
Dependent Claim
22 words
Circuit arrangement as claimed in claim 1, wherein said input means includes register means and said counter means comprises a binary counter.
Claim 4
Dependent Claim
34 words
Circuit arrangement as claimed in claim 1, further comprising an EXCLUSIVE OR gate and wherein the input of said second shift register means is coupled to said input means via said EXCLUSIVE OR gate.
Claim 5
Dependent Claim
47 words
Circuit arrangement as claimed in claim 1, further comprising an AND gate connected between said input means and inputs of said first shift register means for transferring the storage information to said first shift register means under the control of a write signal and an additional signal.
Claim 6
Dependent Claim
53 words
Circuit arrangement as claimed in claim 1, further comprising an AND gate connected between the outputs of said counter means and inputs of said first shift register means for transferring the output of said counter means to said first shift register means under the control of a write signals and an additional signal.
Claim 7
Dependent Claim
57 words
Circuit arrangement as claimed in claim 1, further comprising an AND gate connected between the outputs of said second shift register means and inputs of said first shift register means for transferring the output of said second shift register means to said first shift register means under the control of a write signal and an additional signal.
Claim 8
Dependent Claim
96 words
Circuit arrangement as claimed in claim 1, further comprising an AND gate connected between the outputs of said counter means and an input of said collating means for transferring the output of said counter means to said collating means under the control of a read signal and an additional signal, and another AND gate connected between the outputs of said first shift register means and another input of said collating means for transferring the output of said first shift register means to said collating means under the control of said read signal and an additional signal.
Claim 9
Dependent Claim
100 words
Circuit arrangement as claimed in claim 1, further comprising an AND gate connected between the outputs of said second shift register means and an input of said collating means for transferring the output of said second shift register means to said collating means under the control of a read signal and an addItional signal, and another AND gate connected between the outputs of said first shift register means and another input of said collating means for transferring the output of said first shift register means to said collating means under the control of said read signal and an additional signal.
Claim 10
Dependent Claim
101 words
In a circuit arrangement for checking stored information, an error signal checking system for checking error signals by adding two types of check digits to information of N digits each having T bits, said error signal checking system comprising counter means for counting the bit in the same bit position within each information digit to provide the first check digit; dividing means for dividing all the information of N digits into T small groups composed of digits at intervals of T digits; and shift register means for counting all the bits within said small groups to provide the second check digit.
Claim 11
Dependent Claim
101 words
In a circuit arrangement for checking stored information, an error signal checking system for checking error signals by adding two types of check digits to information of N digits each having T bits, said error signal checking system comprising counter means for counting the bit in the same bit position within each information digit to provide the first check digit; dividing means for dividing all the information of N digits into T small groups composed of digits at intervals of T digits; and shift register means for counting all the bits within said small groups to provide the second check digit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-27 | 1976-08-28 | 1977-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-27 | 1980-08-28 | 1981-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-27 | 1984-08-28 | 1985-02-27 | $7700.00 | Window Closed / Lapsed |