Patent US4340534A successfully refreshed from Google Patents.
Patent US3718853A successfully refreshed from Google Patents.
US3718853A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse width limiting means for inverter circuits
Assignee: General Electric Co
•
Filing: 1971-08-16
•
Granted: 1973-02-27
•
Expires: 1991-08-16
Abstract
Abstract An inverter circuit utilizing gate controlled load rectifiers for changing direct current electric power to alternating current electric power and gate controlled commutating rectifiers for commutating the respective load rectifiers is provided with control apparatus for sensing commutating current during the commutation of a first load rectifier and blocking commutation of a second load rectifier (through the firing or turning ''''on'''' of the respective commutating rectifier) during a blocking time interval including a variable commutation interval during which commutating current is sensed and a fixed delay interval following the commutation interval.
Inventors
- 👤 C Graf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:55
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/505; H02M7/515; H02M7/5152; H02M7/5155; H02M7/525; H02M7/527
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
366 words
In an inverter circuit including at least one set of two series connected load current carrying gate controlled rectifiers connected across a source of direct current electric power, a respective set of two series connected commutating gate controlled rectifiers of similar polarity connected across said source of electric power, and commutating circuit means interconnecting the junction of said two load current carrying gate controlled rectifiers and the junction of said two commutating gate controlled rectifiers, pulse width control means comprising: means fOr sensing commutating current in said commutating circuit means during commutation of either one of said load current carrying gate controlled rectifiers; and blocking means coupled to said current sensing means and responsive to the sensed commutating current for blocking commutation of the other one of said load current carrying gate controlled rectifiers during a blocking time interval comprising the interval during which commutating current is sensed and a fixed delay interval, said blocking means comprising: logic means having first input means for receiving a first input signal when it is desired to turn on a first one of said commutating gate controlled rectifiers and a second input signal when it is desired to turn on a second one of said commutating gate controlled rectifiers, second input means, and output means coupled to said commutating gate controlled rectifiers for supplying a first output signal for causing said first rectifier to turn on and a second output signal for causing said second rectifier to turn on, and means coupled to said second input means and said current sensing means for generating and supplying to said logic means a blocking signal throughout the blocking time interval, said means for generating a blocking signal including timing means responsive to the sensed commutating current for initiating the fixed delay interval at the end of the interval during which commutating current is sensed, said logic means being responsive, in the absence of a blocking signal, to a first input signal to produce a first output signal and to a second input signal to produce a second output signal, and said logic means being responsive to a blocking signal to block the production of output signals in response to input signals.
Claim 2
Dependent Claim
366 words
In an inverter circuit including at least one set of two series connected load current carrying gate controlled rectifiers connected across a source of direct current electric power, a respective set of two series connected commutating gate controlled rectifiers of similar polarity connected across said source of electric power, and commutating circuit means interconnecting the junction of said two load current carrying gate controlled rectifiers and the junction of said two commutating gate controlled rectifiers, pulse width control means comprising: means fOr sensing commutating current in said commutating circuit means during commutation of either one of said load current carrying gate controlled rectifiers; and blocking means coupled to said current sensing means and responsive to the sensed commutating current for blocking commutation of the other one of said load current carrying gate controlled rectifiers during a blocking time interval comprising the interval during which commutating current is sensed and a fixed delay interval, said blocking means comprising: logic means having first input means for receiving a first input signal when it is desired to turn on a first one of said commutating gate controlled rectifiers and a second input signal when it is desired to turn on a second one of said commutating gate controlled rectifiers, second input means, and output means coupled to said commutating gate controlled rectifiers for supplying a first output signal for causing said first rectifier to turn on and a second output signal for causing said second rectifier to turn on, and means coupled to said second input means and said current sensing means for generating and supplying to said logic means a blocking signal throughout the blocking time interval, said means for generating a blocking signal including timing means responsive to the sensed commutating current for initiating the fixed delay interval at the end of the interval during which commutating current is sensed, said logic means being responsive, in the absence of a blocking signal, to a first input signal to produce a first output signal and to a second input signal to produce a second output signal, and said logic means being responsive to a blocking signal to block the production of output signals in response to input signals.
Claim 3
Dependent Claim
57 words
Pulse width control means as defined by claim 1 in which said means for generating a blocking signal includes timing means for establishing the fixed delay interval, said timing means being responsive to the sensed commutating current such that the fixed delay interval is initiated at the end of the interval during which commutating current is sensed.
Claim 4
Dependent Claim
36 words
Pulse width control means as defined by claim 2 in which said means for generating a blocking signal comprises circuit means and in which said timing means is an energy storage element in said circuit means.
Claim 5
Dependent Claim
133 words
Pulse width control means as defined by claim 1 in which said means for generating a blocking signal comprises: a resistive circuit connected across a source of direct current electric power, said resistive circuit including switching means having current blocking and current conducting states, and means connected to said switching means for shifting and switching means between said two states, said shifting means normally maintaining said switching means in a first one of said states and being responsive to the sensed commutating current to shift said switching means to a second one of said states throughout the blocking time interval, said blocking signal being a voltage signal produced at a preselected point in said resistive circuit at which a change in the states of said switching means results in a substantial voltage change.
Claim 6
Dependent Claim
36 words
Pulse width control means as defined by claim 4 in which said switching means is a transistor, said shifting means controlling the state of said transistor by the selective application of electric signals to it base.
Claim 7
Dependent Claim
201 words
Pulse width control means as defined by claim 2 in which said timing means comprises an energy storage devices and in which said means for generating a blocking signal further comprises: first circuit means connected across a source of direct current electric power, said first circuit means including switching means having current blocking and current conducting states, and second circuit means coupled to said current sensing means, said energy storage device, and said switching means of said first circuit means for shifting said switching means between said two states by thE application of electric signals thereto, said second circuit means normally maintaining said switching means of said first circuit means in a first one of said states and being responsive to the sense commutating current to shift said switching means to a second one of said states at the initiation of commutation, said energy storage device being effective to maintain said switching means in said second state for the fixed delay interval following the completion of commutation, said blocking signal being a voltage signal produced at a preselected point in said first circuit means at which a change in the state of said switching means results in a substantial voltage change.
Claim 8
Dependent Claim
35 words
Commutation control means as defined by claim 6 in which the switching means of said first circuit means is a transistor having a base connected to said second circuit means for receiving electric signals therefrom.
Claim 9
Dependent Claim
18 words
Commutation control means as defined by claim 7 in which said current sensing means is a current transformer.
Claim 10
Dependent Claim
49 words
Commutation control means as defined by claim 1 in which said logic means further comprises feedback means coupling said output means and said second input means for supplying a blocking signal to said second input means substantially simultaneously with the production of an output signal at said output means.
Claim 11
Dependent Claim
20 words
Commutation control means as defined by claim 1 in which said logic means comprises a plurality of interconnected NAND-NOR gates.
Claim 12
Dependent Claim
49 words
Commutation control means as defined by claim 8 in which said logic means further comprises feedback means coupling said output means and said second input means for supplying a blocking signal to said second input means substantially simultaneously with the production of an output signal at said output means.
Claim 13
Dependent Claim
20 words
Commutation control means as defined by claim 11 in which said logic means comprises a plurality of interconnected NAND-NOR gates.
Claim 14
Dependent Claim
17 words
Commutation control means as defined by claim 3 in which said energy storage element is a capacitor.
Claim 15
Dependent Claim
18 words
Commutation control means as defined by claim 13 in which said current sensing means is a current transformer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-27 | 1976-08-28 | 1977-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-27 | 1980-08-28 | 1981-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-27 | 1984-08-28 | 1985-02-27 | $7700.00 | Window Closed / Lapsed |