Patent US2162722A successfully refreshed from Google Patents.
Patent US1930357A successfully refreshed from Google Patents.
Patent US3718780A successfully refreshed from Google Patents.
US3718780A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Active pulse transmission circuit for an integrated circuit
Assignee: Hitachi Ltd
•
Filing: 1971-02-23
•
Granted: 1973-02-27
•
Expires: 1991-02-23
Abstract
Abstract An active pulse transmission circuit for an integrated circuit comprising a plurality of T-shaped networks connected in series to each other, each having series input and output resistances and a parallel combination of a capacitance and a negative resistance device comprising two transistors cross-connected to each other and a plurality of resistances.
Inventors
- 👤 Y Oya
- 👤 A Hayasaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:13
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H04; H04B; H04B3/00; H04B3/02; H04B3/04; H04B3/16; H04B3/18; H10D84/80; H10D84/811; H10D84/817
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
210 words
An active pulse transmission circuit adapted to be forming into an integrated circuit comprising: a plurality of negative resistance devices, each comprising first and second transistors each of which has an emitter, a collector and a base, the collector and base of each transistor being connected respectively to the base and collector of the other transistor, said collectors also being connected to a direct current voltage source, said device having a symmetrical construction with respect to a point between said collectors with which said voltage source is connected and at least one pair of first and second terminals derived from any given junction points in the device; a plurality of capacitors connected in parallel with respective ones of said devices across said pair of first and second terminals; a common conductor with which said first terminal is connected; at least one group of resistance elements, each resistance element being connected between said second terminals of respective adjacent ones of said devices; at least one pair of input terminals connected respectively to said first and second terminals of a first one of said devices; and at least one pair of output terminals connected respectively to said first and second terminals of any one of said devices other than said first one.
Claim 2
Dependent Claim
210 words
An active pulse transmission circuit adapted to be forming into an integrated circuit comprising: a plurality of negative resistance devices, each comprising first and second transistors each of which has an emitter, a collector and a base, the collector and base of each transistor being connected respectively to the base and collector of the other transistor, said collectors also being connected to a direct current voltage source, said device having a symmetrical construction with respect to a point between said collectors with which said voltage source is connected and at least one pair of first and second terminals derived from any given junction points in the device; a plurality of capacitors connected in parallel with respective ones of said devices across said pair of first and second terminals; a common conductor with which said first terminal is connected; at least one group of resistance elements, each resistance element being connected between said second terminals of respective adjacent ones of said devices; at least one pair of input terminals connected respectively to said first and second terminals of a first one of said devices; and at least one pair of output terminals connected respectively to said first and second terminals of any one of said devices other than said first one.
Claim 3
Dependent Claim
74 words
An active pulse transmission circuit according to claim 1, wherein each of said devices has one pair of first and second terminals, said resistance elements are provided in one group for said second terminals of said pairs of respective ones of said devices, and thus each of said pair of input terminals and said pair of output terminals is provided in one pair, whereby a pulse of one kind is transmitted at a time.
Claim 4
Dependent Claim
40 words
An active pulse transmission circuit acCording to claim 2, wherein each of said devices has an emitter resistor connected to the emitter of said first transistor, and said pair of first and second terminals are derived across said emitter resistor.
Claim 5
Dependent Claim
86 words
An active pulse transmission circuit according to claim 1, wherein each of said devices has two pairs of first and second terminals provided respectively in the symmetrical halves of the device, said resistance elements are provided in two groups respectively for said second terminals of said two pairs of respective ones of said devices, and thus each of said pair of input terminals and said pair of output terminals is provided in two pairs, whereby pulses having two kinds of polarity are transmitted at a time.
Claim 6
Dependent Claim
44 words
An active pulse transmission circuit according to claim 4, wherein each of said devices has emitter resistors connected respectively to the emitters of said first and second transistors, and said two pairs of first and second terminals are derived across said emitter resistors, respectively.
Claim 7
Dependent Claim
171 words
An active pulse transmission circuit adapted to be formed into an integrated circuit comprising: first and second input terminals; first and second output terminals; first means for coupling said first input terminal to said first output terminal; second means for coupling said second input terminal to said second output terminal; a negative resistance element connected between said first and second means, including first and second transistors, each of which comprises an input electrode, an output electrode, and a control electrode, the respective control and output electrodes of said first and second transistors being D. C. coupled to one another, while at least one of said first and second transistors has its input electrode connected to one of said first and second means, and means for connecting a source of D. C. voltage to the output electrodes of each of said first and second transistors; and third means for D. C. coupling the input electrode of one of said first and second transistors to the other of said first and second means.
Claim 8
Dependent Claim
171 words
An active pulse transmission circuit adapted to be formed into an integrated circuit comprising: first and second input terminals; first and second output terminals; first means for coupling said first input terminal to said first output terminal; second means for coupling said second input terminal to said second output terminal; a negative resistance element connected between said first and second means, including first and second transistors, each of which comprises an input electrode, an output electrode, and a control electrode, the respective control and output electrodes of said first and second transistors being D. C. coupled to one another, while at least one of said first and second transistors has its input electrode connected to one of said first and second means, and means for connecting a source of D. C. voltage to the output electrodes of each of said first and second transistors; and third means for D. C. coupling the input electrode of one of said first and second transistors to the other of said first and second means.
Claim 9
Dependent Claim
67 words
An active pulse transmission circuit according to claim 6, wherein said first means comprises first and second resistance elements connected between said first input terminal and said first output terminal, the common connection of said first and second resistance elements being connected to said negative resistance element, and wherein said second means comprises a conductor for directly connecting said second input terminal to said second output terminal.
Claim 10
Dependent Claim
27 words
An active pulse transmission circuit according to claim 7, further including a capacitor connected in parallel with said negative resistance element between said first and second means.
Claim 11
Dependent Claim
40 words
An active pulse transmission circuit according to claim 6, wherein said third means comprises a resistor element connected between the input electrode of said one of said first and second transistors and the other of said first and second means.
Claim 12
Dependent Claim
40 words
An active pulse transmission circuit according to claim 8, wherein said third means comprises a resistor element connected between the input electrode of said one of said first and second transistors and the other of said first and second means.
Claim 13
Dependent Claim
29 words
An active pulse transmission circuit according to claim 6, wherein the input electrodes of said first and second transistors are respectively connected directly to said first and second means.
Claim 14
Dependent Claim
34 words
An active pulse transmission circuit according to claim 11, further including first and second resistance elements respectively connected between the input electrodes of said first and second transistors and a source of reference potential.
Claim 15
Dependent Claim
35 words
An active pulse transmission circuit according to claim 12, wherein said first and second means each comprises means for respectively directly connecting said first and second input electrodes to said first and second output electrodes.
Claim 16
Dependent Claim
35 words
An active pulse transmission circuit according tO claim 13, further including first and second resistors and capacitors connected in series between each of said first and second output terminals and said source of reference potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-27 | 1976-08-28 | 1977-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-27 | 1980-08-28 | 1981-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-27 | 1984-08-28 | 1985-02-27 | $7700.00 | Window Closed / Lapsed |