Patent US3717515A successfully refreshed from Google Patents.
US3717515A
Expired / Lapsed
US
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Process for fabricating a pedestal transistor
Assignee: International Business Machines Corp
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Filing: 1969-11-10
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Granted: 1973-02-20
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Expires: 1989-11-10
Abstract
Abstract This invention relates to a process for fabricating monolithic integrated circuits including at least one pedestal transistor device and comprises the steps of selectively forming and removing oxide layers to produce a substrate having a raised pedestal structure, diffusing a high conductivity impurity into the substrate so as to form a subcollector region having a pedestal portion, growing and then forming a flat epitaxial collector region over said subcollector region, using oxide conversion to remove the raised region, and successively diffusing a base and emitter region over the pedestal region.
Inventors
- 👤 K Ashar
- 👤 L Maheux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/043; Y10S148/085; Y10S148/117; Y10S148/145
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
267 words
A method for fabricating a monolithic integrated circuit including at least one pedestal transistor device using a single epitaxial layer process comprising the steps of: a. providing a substrate of a first conductivity type, b. forming a raised pedestal region on said substrate by forming an oxide layer and an overlying masking layer on said substrate in an area substantially conforming to said pedestal region, the masking layer being selected to limit thermal growth thereunder, and then converting selected non-pedestal regions of the original substrate to an oxide and then removing the oxide and masking layer, c. diffusing an impurity of a second conductivity type into a limited surface area larger than and encompassing said pedestal region, said second conductivity type being opposite to said first conductivity type, so as to convert a second region of the substrate to a second conductivity type, said second region constituting a pedestal subcollector region, d. growing and forming a substantially flat epitaxial layer over said pedestal region by removing a reproduced pedestal region formed on the upper surface of the epitaxial layer, removing said reproduced pedestal region formed on the upper surface of the epitaxial layer by converting said reproduced pedestal region to an oxide, and etching away said converted oxide, e. forming said substantially flat epitaxial layer of a material having a higher resistivity than said pedestal subcollector region, f. diffusing a base region into said epitaxial collector layer over said subcollector pedestal region, and g. diffusing an emitter region into said base region so as to define a base-emitter junction located substantially coextensive with the pedestal subcollector region.
Claim 2
Independent Claim
267 words
A method for fabricating a monolithic integrated circuit including at least one pedestal transistor device using a single epitaxial layer process comprising the steps of: a. providing a substrate of a first conductivity type, b. forming a raised pedestal region on said substrate by forming an oxide layer and an overlying masking layer on said substrate in an area substantially conforming to said pedestal region, the masking layer being selected to limit thermal growth thereunder, and then converting selected non-pedestal regions of the original substrate to an oxide and then removing the oxide and masking layer, c. diffusing an impurity of a second conductivity type into a limited surface area larger than and encompassing said pedestal region, said second conductivity type being opposite to said first conductivity type, so as to convert a second region of the substrate to a second conductivity type, said second region constituting a pedestal subcollector region, d. growing and forming a substantially flat epitaxial layer over said pedestal region by removing a reproduced pedestal region formed on the upper surface of the epitaxial layer, removing said reproduced pedestal region formed on the upper surface of the epitaxial layer by converting said reproduced pedestal region to an oxide, and etching away said converted oxide, e. forming said substantially flat epitaxial layer of a material having a higher resistivity than said pedestal subcollector region, f. diffusing a base region into said epitaxial collector layer over said subcollector pedestal region, and g. diffusing an emitter region into said base region so as to define a base-emitter junction located substantially coextensive with the pedestal subcollector region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-20 | 1976-08-21 | 1977-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-20 | 1980-08-21 | 1981-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-20 | 1984-08-21 | 1985-02-20 | $7700.00 | Window Closed / Lapsed |