Code conversion circuit for a two-level to multi-level code converter

Claim 1

A code conversion circuit for a two-level to multilevel code conversion apparatus wherein n two-level code inputs (n being a positive integer) are converted to multilevel code outputs whose number of levels is equal to or greater than 2n, comprising first conversion means for converting said n two-level code inputs to intermediate n two-level code signals including n mark-ratio counters for respectively examining the mark-ratio of each of said n two-level code inputs in a predetermined time period, n read-out circuits for respectively reading out selectively predetermined ones of the true and complementary outputs of the most significant digits of said mark-ratio counters, n holding circuits for respectively holding the output of said read-out circuits during said predetermined time period, n delay circuits for delaying said two-level code inputs by said predetermined time period, n exclusive-OR circuits for respectively producing a logical discoincidence output between each output of said delay circuits and each output of the associated one of said holding circuits, and a timing circuit for supplying timing pulses to said read-out circuits and said holding circuits; and second means for converting said intermediate n two-level code signals to said multilevel code outputs, whereby the occurrence frequency of a particular level of said multilevel code outputs is made highest among the levels of the multilevel code outputs by the selectively predetermined combination of said most significant digit outputs.