Binary to multilevel conversion by combining redundant information signal with transition encoded information signal

Abstract

Abstract 1,069,930. Telegraphy. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 20, 1965 [Oct. 16, 1964], No. 39957/65. Heading H4P. In a data transmission system binary signals are converted into multi-level signals by selecting a first group of signals from the input word and developing from them a succession of signals in a first channel, means for selecting ,a second group and for developing a succession of signals in a second channel, the amplitude of the output signal being determined by the level of the signal in the first channel, and the polarity by the level of the signal in the second channel. The circuit, Fig. 1 (not shown), comprises three triggers (ACT1-ACT3) connected as a shift register to which the input signals 4 are applied (Fig. 2, not shown). The pattern is shifted by clock pulses (1). The clock pulses also pass through trigger (ACT4) to produce double length clock pulses and in trigger (ACT5) they are doubled again. The output (5) from trigger (ACT 1) is inverted and gated with the output of trigger (ACT5). The resulting signal (13) is the second two pulses of the input word, inverted. The output of the trigger (ACT3) is inverted and gated with the output (3) of trigger (ACT5) inverted. This selects on lead 14 the same two bits inverted but delayed by half the word length. These two signals are combined in Or gate (3) and signal (15) consists of the second pair of bits in the input word, inverted and repeated. This signal is inverted and applied to the combining circuit. By similar gating arrangements the first two bits are selected and combined to stretch each to double length (8, Fig. 2). This signal is' applied to a first transition coder (CT1) and then to another (CT2). The output is delayed and inverted (RET1) and recombined to form a signal (12) which is used in the combining circuit (COM) to control the sign of the output signal 16. The output signals (16) consists of a large magnitude for " 1 " and a small magnitude for " 0." This sequence is repeated twice to represent the second pair of digits in the input word and the polarity of these signals indicates the first two digits.

Inventors

• 👤 Michael Constantine Melas

Bibliographic Details