Patent US3716725A successfully refreshed from Google Patents.
US3716725A
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US
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Ring counter
Assignee: Chicago Musical Instrument Co
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Filing: 1971-01-04
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Granted: 1973-02-13
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Expires: 1991-01-04
Abstract
Abstract An electronic ring counter driven by a source of pulses and having controls to bypass some of the stages of the ring counter, each stage employing a single transistor.
Inventors
- 👤 A Freeman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:48
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; G; G10; G10H; G10H1/00; G10H1/36; G10H1/40; H03K23/58; H03K23/588
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
191 words
A ring counter for counting successive pulse signals, comprising: a. at least three stages connected in a ring, each of said stages comprising: 1. a single bipolar transistor, said transistor being the sole active element in said stage, 2. a set of resistors connecting the collector of said transistor to the bases of the transistors of the other stages, 3. a reactive coupling from the collector of said transistor to the base of the succeeding transistor, 4. a resistive load connected to the collector of said transistor and adapted to be connected to a source of potential, and 5. the emitter of said transistor being connected to a voltage reference, whereby all but one of the transistors remains conductive; and b. input terminal means coupled to the bases of said transistors for receiving the pulse signals, said one transistor when nonconductive being always rendered conductive in response to the next one of said pulse signals, and the following transistor being thereby rendered nonconductive so that one count is obtained each time that any of said stages becomes nonconductive; and c. output terminal means coupled to at least one of said stages.
Claim 2
Dependent Claim
191 words
A ring counter for counting successive pulse signals, comprising: a. at least three stages connected in a ring, each of said stages comprising: 1. a single bipolar transistor, said transistor being the sole active element in said stage, 2. a set of resistors connecting the collector of said transistor to the bases of the transistors of the other stages, 3. a reactive coupling from the collector of said transistor to the base of the succeeding transistor, 4. a resistive load connected to the collector of said transistor and adapted to be connected to a source of potential, and 5. the emitter of said transistor being connected to a voltage reference, whereby all but one of the transistors remains conductive; and b. input terminal means coupled to the bases of said transistors for receiving the pulse signals, said one transistor when nonconductive being always rendered conductive in response to the next one of said pulse signals, and the following transistor being thereby rendered nonconductive so that one count is obtained each time that any of said stages becomes nonconductive; and c. output terminal means coupled to at least one of said stages.
Claim 3
Dependent Claim
14 words
a single bipolar transistOr, said transistor being the sole active element in said stage,
Claim 4
Dependent Claim
14 words
a single bipolar transistOr, said transistor being the sole active element in said stage,
Claim 5
Dependent Claim
23 words
A ring counter for counting successive pulse signals, comprising: a. at least three stages connected in a ring, each of said stages comprising:
Claim 6
Dependent Claim
23 words
A ring counter for counting successive pulse signals, comprising: a. at least three stages connected in a ring, each of said stages comprising:
Claim 7
Dependent Claim
14 words
a single bipolar transistor, said transistor being the sole active element in said stage,
Claim 8
Dependent Claim
14 words
a single bipolar transistor, said transistor being the sole active element in said stage,
Claim 9
Dependent Claim
20 words
a set of resistors connecting the collector of said transistor to the bases of the transistors of the other stages,
Claim 10
Dependent Claim
20 words
a set of resistors connecting the collector of said transistor to the bases of the transistors of the other stages,
Claim 11
Dependent Claim
45 words
A ring counter for counting successive pulse signals, comprising: a. an even number of at least four stages connected in a ring, alternate ones of the successive stages comprising a first group and the other stages comprising a second group, each of said stages comprising:
Claim 12
Dependent Claim
45 words
A ring counter for counting successive pulse signals, comprising: a. an even number of at least four stages connected in a ring, alternate ones of the successive stages comprising a first group and the other stages comprising a second group, each of said stages comprising:
Claim 13
Dependent Claim
24 words
a set of resistors connecting the collector of said transistor to the bases of the transistors of the other stages in the same group,
Claim 14
Dependent Claim
24 words
a set of resistors connecting the collector of said transistor to the bases of the transistors of the other stages in the same group,
Claim 15
Dependent Claim
21 words
a resistive load connected to the collector of said transistor and adapted to be connected to a source of potential, and
Claim 16
Dependent Claim
21 words
a resistive load connected to the collector of said transistor and adapted to be connected to a source of potential, and
Claim 17
Dependent Claim
21 words
a resistive load connected to the collector of said transistor and adapted to be connected to a source of potential, and
Claim 18
Dependent Claim
21 words
a resistive load connected to the collector of said transistor and adapted to be connected to a source of potential, and
Claim 19
Dependent Claim
92 words
the emitter of said transistor being connected to a voltage reference, whereby all but one of the transistors remains conductive; and b. input terminal means coupled to the bases of said transistors for receiving the pulse signals, said one transistor when nonconductive being always rendered conductive in response to the next one of said pulse signals, and the following transistor being thereby rendered nonconductive so that one count is obtained each time that any of said stages becomes nonconductive; and c. output terminal means coupled to at least one of said stages.
Claim 20
Dependent Claim
92 words
the emitter of said transistor being connected to a voltage reference, whereby all but one of the transistors remains conductive; and b. input terminal means coupled to the bases of said transistors for receiving the pulse signals, said one transistor when nonconductive being always rendered conductive in response to the next one of said pulse signals, and the following transistor being thereby rendered nonconductive so that one count is obtained each time that any of said stages becomes nonconductive; and c. output terminal means coupled to at least one of said stages.
Claim 21
Dependent Claim
93 words
the emitter of said transistor being connected to a voltage reference, whereby all but one of the transistors remains conductive; and b. two input terminal means coupled to the bases of said transistors for receiving the pulse signals, said one transistor when nonconductive being always rendered conductive in response to the next one of said pulse signals, and the following transistor being thereby rendered nonconductive so that one count is obtained each time that any of said stages becomes nonconductive; and c. output terminal means coupled to at least one of said stages.
Claim 22
Dependent Claim
93 words
the emitter of said transistor being connected to a voltage reference, whereby all but one of the transistors remains conductive; and b. two input terminal means coupled to the bases of said transistors for receiving the pulse signals, said one transistor when nonconductive being always rendered conductive in response to the next one of said pulse signals, and the following transistor being thereby rendered nonconductive so that one count is obtained each time that any of said stages becomes nonconductive; and c. output terminal means coupled to at least one of said stages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-13 | 1976-08-14 | 1977-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-13 | 1980-08-14 | 1981-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-13 | 1984-08-14 | 1985-02-13 | $7700.00 | Window Closed / Lapsed |