Patent US3715729A successfully refreshed from Google Patents.
US3715729A
Expired / Lapsed
US
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Timing control for a multiprocessor system
Assignee: International Business Machines Corp
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Filing: 1971-03-10
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Granted: 1973-02-06
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Expires: 1991-03-10
Abstract
Abstract A multiprocessor system has plural autonomous digital data processors operable to communicate individually with a common storage system. Each processor has its own clock. The timing control means selectively uses any one of the individual processor clocks for timing the communication of its or any other processor with the common storage system.
Inventors
- 👤 B Mercy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F1/00; G06F1/04; G06F1/12; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
94 words
In a multiprocessor system, the combination comprising: plural digital data processors each having timing means operable to provide timing for their respective processors; a system element shared by said processors; means forming a channel for communicating data between said processors and said shared system element; and control means for timing the transmission of data over said channel between said shared system element and said processors including selection means operable for selecting a timing means of one of said processors for timing the communication of data between another of said processors and said system element.
Claim 2
Dependent Claim
94 words
In a multiprocessor system, the combination comprising: plural digital data processors each having timing means operable to provide timing for their respective processors; a system element shared by said processors; means forming a channel for communicating data between said processors and said shared system element; and control means for timing the transmission of data over said channel between said shared system element and said processors including selection means operable for selecting a timing means of one of said processors for timing the communication of data between another of said processors and said system element.
Claim 3
Dependent Claim
94 words
In a multiprocessor system, the combination comprising: plural digital data processors each having timing means operable to provide timing for their respective processors; a system element shared by said processors; MEANS forming a channel for communicating data between said processors and said shared system element; and control means for timing the transmission of data over said channel between said shared system element and said processors including selection means operable for selecting a timing means of one of said processors for timing the communication of data between another of said processors and said system element.
Claim 4
Dependent Claim
94 words
In a multiprocessor system, the combination comprising: plural digital data processors each having timing means operable to provide timing for their respective processors; a system element shared by said processors; MEANS forming a channel for communicating data between said processors and said shared system element; and control means for timing the transmission of data over said channel between said shared system element and said processors including selection means operable for selecting a timing means of one of said processors for timing the communication of data between another of said processors and said system element.
Claim 5
Dependent Claim
48 words
A multiprocessor system in accordance with claim 1 in which said selection means is operable for selecting a timing means of one of said processors for timing the communication of data between either said one of said processors or another of said processors and said shared system element.
Claim 6
Dependent Claim
77 words
A multiprocessor system in accordance with claim 2 in which said selection means comprises means for determining whether a timing means of one of said processors is in operation for supplying timing pulses for communication of data, and means responsive to said determining means for deciding whether to hold said timing means of said one of said processors in service or to use the timing means of said another of said processors for successive communications of data.
Claim 7
Dependent Claim
88 words
A multiprocessor system in accordance with claim 3 in which said processors generate command signals for communicating data with said shared system element; and said timing control means further includes means for generating a busy signal if one of said processors is in communication with said shared system element; and said decision means includes means responsive to said processor commands and said busy signal as a basis for holding a timing means of one of said processors or changing to a timing means of another of said processors.
Claim 8
Dependent Claim
60 words
A multiprocessor system in accordance with claim 4 in which said decision means is operable in response to coincident processor command signal and said busy signal to hold said timing means of said one of said processors in communication with said shared system element for timing a subsequent communication of said another of said processors with said shared system element.
Claim 9
Dependent Claim
52 words
A multiprocessor system in accordance with claim 4 in which said decision means is operable in response to a processor command signal in the absence of a busy signal to select the timing means of said processor generating said command signal to time the communication of data with said shared system element.
Claim 10
Dependent Claim
60 words
A multiprocessor system in accordance with claim 1 in which said processors are essentially autonomous digital data processing apparatus; said timing means include clock devices operable to generate sequential timing pulses, independently to said processors, and said shared system element is a system storage means connected to said channel means for storing and retrieving digital data processable by said processors.
Claim 11
Dependent Claim
54 words
A multiprocessor system in accordance with claim 7 in which said system storage means includes a storage clock means for timing storage and retrieval of digital data transmissible via said channel means; and said timing control means includes means for initiating the operation of said storage clock means in synchronism with said clock devices.
Claim 12
Dependent Claim
43 words
A multiprocessor system in accordance with claim 8 in which said clock devices have identical operating timing cycles and said storage clock means has an operation cycle which is equal to or a multiple of said operating timing cycle of said clock devices.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-06 | 1976-08-07 | 1977-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-06 | 1980-08-07 | 1981-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-06 | 1984-08-07 | 1985-02-06 | $7700.00 | Window Closed / Lapsed |