Patent US3714654A successfully refreshed from Google Patents.
US3714654A
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Ecm pulse analyzer
Assignee: United States Department of the Navy
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Filing: 1972-01-06
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Granted: 1973-01-30
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Expires: 1992-01-06
Abstract
Abstract ECM pulse analyzer apparatus for automatically measuring pulse repetition frequency (PRF) and pulsewidth (PW) of incoming pulsed signals received by ECM receivers. Pulsewidth is measured by dual-threshold circuitry which eliminates noise effects by means of a high threshold level which sorts pulses for minimum amplitude and a lower threshold level at which pulsewidth is measured when a pulse exceeds the higher threshold. Pulse repetition frequency is measured by counting PRI during the two periods between the three pulses and converting PRI into PRF by counting up to the stored PRI value at a known rate in a predetermined time period whereby the number of times that the count can proceed is equal to the PRF corresponding to the stored PRI.
Inventors
- 👤 S Wicks
- 👤 R Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:41
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/021; G01R; G01R23/00; G01R23/02; G01R23/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
312 words
In ECM receiver systems, apparatus for automatically measuring pulsewidth and pulse repetition frequency of incoming video pulses, comprising: dual threshold means for receiving said video pulses and being responsive thereto to measure pulsewidth at a first threshold level only if the amplitude thereof is substantially equal to or exceeds a higher, second threshold level, to thereby produce a pulsewidth measurement pulse; first logic gate means for receiving the output of said dual-threshold means for three successive video pulses; first binary counter means for receiving the output of said logic gate means and for storing three successive pulsewidth measurement pulses; display means for receiving the output of said first binary counter means to thereby display said three successive pulsewidth measurement pulses; second binary counter means for receiving the output of said dual-threshold means and for producing successive, first and second pulse repetition interval counts for the first and second of said three successive video pulses; shift register means for successively receiving the output of said second binary counter means and for storing successively said first and second pulse repetition interval counts for a first selectively predetermined time period; clock means for providing a selectively predetermined clock signal; third binary counter means for receiving said clock signal, for a second selectively predetermined time period; comparator means for receiving the successive outputs from said shift register means and the output from said third binary counter means at the end of said second selectively predetermined time period and for providing an output pulse when both said outputs are substantially equal; fourth binary counter means for receiving successively said output pulse and for producing an output substantially equal to the pulse repetition frequency of said successive video pulses; said fourth binary counter means being connected at its output to said display means; and said third binary counter means being connected to the output of said comparator means.
Claim 2
Dependent Claim
312 words
In ECM receiver systems, apparatus for automatically measuring pulsewidth and pulse repetition frequency of incoming video pulses, comprising: dual threshold means for receiving said video pulses and being responsive thereto to measure pulsewidth at a first threshold level only if the amplitude thereof is substantially equal to or exceeds a higher, second threshold level, to thereby produce a pulsewidth measurement pulse; first logic gate means for receiving the output of said dual-threshold means for three successive video pulses; first binary counter means for receiving the output of said logic gate means and for storing three successive pulsewidth measurement pulses; display means for receiving the output of said first binary counter means to thereby display said three successive pulsewidth measurement pulses; second binary counter means for receiving the output of said dual-threshold means and for producing successive, first and second pulse repetition interval counts for the first and second of said three successive video pulses; shift register means for successively receiving the output of said second binary counter means and for storing successively said first and second pulse repetition interval counts for a first selectively predetermined time period; clock means for providing a selectively predetermined clock signal; third binary counter means for receiving said clock signal, for a second selectively predetermined time period; comparator means for receiving the successive outputs from said shift register means and the output from said third binary counter means at the end of said second selectively predetermined time period and for providing an output pulse when both said outputs are substantially equal; fourth binary counter means for receiving successively said output pulse and for producing an output substantially equal to the pulse repetition frequency of said successive video pulses; said fourth binary counter means being connected at its output to said display means; and said third binary counter means being connected to the output of said comparator means.
Claim 3
Dependent Claim
312 words
In ECM receiver systems, apparatus for automatically measuring pulsewidth and pulse repetition frequency of incoming video pulses, comprising: dual threshold means for receiving said video pulses and being responsive thereto to measure pulsewidth at a first threshold level only if the amplitude thereof is substantially equal to or exceeds a higher, second threshold level, to thereby produce a pulsewidth measurement pulse; first logic gate means for receiving the output of said dualthreshold means for three successive video pulses; first binary counter means for receiving the output of said logic gate means and for storing three successive pulsewidth measurement pulses; display means for receiving the output of said first binary counter means to thereby display said three successive pulsewidth measurement pulses; second binary counter means for receiving the output of said dual-threshold means and for producing successive, first and second pulse repetition interval counts for the first and second of said three successive video pulses; shift register means for successively receiving the output of said second binary counter means and for storing successively said first and second pulse repetition interval counts for a first selectively predetermined time period; clock means for providing a selectively predetermined clock signal; third binary counter means for receiving said clock signal, for a second selectively predetermined time period; comparator means for receiving the successive outputs from said shift register means and the output from said third binary counter means at the end of said second selectively predetermined time period and for providing an output pulse when both said outputs are substantially equal; fourth binary counter means for receiving successively said output pulse and for producing an output substantially equal to the pulse repetition frequency of said successive video pulses; said fourth binary counter means being connected at its output to said display means; and said third binary counter means being connected to the output of said comparator means.
Claim 4
Dependent Claim
312 words
In ECM receiver systems, apparatus for automatically measuring pulsewidth and pulse repetition frequency of incoming video pulses, comprising: dual threshold means for receiving said video pulses and being responsive thereto to measure pulsewidth at a first threshold level only if the amplitude thereof is substantially equal to or exceeds a higher, second threshold level, to thereby produce a pulsewidth measurement pulse; first logic gate means for receiving the output of said dualthreshold means for three successive video pulses; first binary counter means for receiving the output of said logic gate means and for storing three successive pulsewidth measurement pulses; display means for receiving the output of said first binary counter means to thereby display said three successive pulsewidth measurement pulses; second binary counter means for receiving the output of said dual-threshold means and for producing successive, first and second pulse repetition interval counts for the first and second of said three successive video pulses; shift register means for successively receiving the output of said second binary counter means and for storing successively said first and second pulse repetition interval counts for a first selectively predetermined time period; clock means for providing a selectively predetermined clock signal; third binary counter means for receiving said clock signal, for a second selectively predetermined time period; comparator means for receiving the successive outputs from said shift register means and the output from said third binary counter means at the end of said second selectively predetermined time period and for providing an output pulse when both said outputs are substantially equal; fourth binary counter means for receiving successively said output pulse and for producing an output substantially equal to the pulse repetition frequency of said successive video pulses; said fourth binary counter means being connected at its output to said display means; and said third binary counter means being connected to the output of said comparator means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |