Patent US3714637A successfully refreshed from Google Patents.
US3714637A
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Monolithic memory utilizing defective storage cells
Assignee: International Business Machines Corp
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Filing: 1970-09-30
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Granted: 1973-01-30
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Expires: 1990-09-30
Abstract
Abstract Transformation logic is provided in the addressing portion of a computer memory to permit the memory to be constructed of components containing defective bit cells. In the production of monolithic memory chips used in computer storage devices, a certain percentage is rejected in production as containing one or more defective bit cells on the chip. This apparatus arranges the almost perfect chips on a memory bit card so that all of the bit cards of a particular memory product are identical as to those sections containing defective bit cells. The valid cells are logically arranged in contiguous address locations by transformation logic which converts the address before it is presented to the memory bit cards. This circuitry places the defective bit positions in high order address locations which are not accessed.
Inventors
- 👤 W Beausoleil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:47
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C8/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
143 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of units containing a plurality of addressable memory cells, which method utilizes partially defective units comprising the steps of: sorting said units into perfect, partially defective, and defective units; sorting said partially defective units into classes based upon which cells of the units are defective; physically arranging said units in said memory according to units that are identical as to which areas have defective cells and which do not, so that units in the same class are placed in the said relative position in said memory; and translating contiguous addresses presented to said memory so that cells in said units containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 2
Independent Claim
143 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of units containing a plurality of addressable memory cells, which method utilizes partially defective units comprising the steps of: sorting said units into perfect, partially defective, and defective units; sorting said partially defective units into classes based upon which cells of the units are defective; physically arranging said units in said memory according to units that are identical as to which areas have defective cells and which do not, so that units in the same class are placed in the said relative position in said memory; and translating contiguous addresses presented to said memory so that cells in said units containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 3
Independent Claim
143 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of units containing a plurality of addressable memory cells, which method utilizes partially defective units comprising the steps of: sorting said units into perfect, partially defective, and defective units; sorting said partially defective units into classes based upon which cells of the units are defective; physically arranging said units in said memory according to units that are identical as to which areas have defective cells and which do not, so that units in the same class are placed in the said relative position in said memory; and translating contiguous addresses presented to said memory so that cells in said units containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 4
Independent Claim
143 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of units containing a plurality of addressable memory cells, which method utilizes partially defective units comprising the steps of: sorting said units into perfect, partially defective, and defective units; sorting said partially defective units into classes based upon which cells of the units are defective; physically arranging said units in said memory according to units that are identical as to which areas have defective cells and which do not, so that units in the same class are placed in the said relative position in said memory; and translating contiguous addresses presented to said memory so that cells in said units containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 5
Independent Claim
143 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of addressable memory cells, which method utilizes partially defective chips comprising the steps of: sorting said chips into perfect, partially defective, and defective chips; sorting said partially defective chips into classes based upon which cells of the chips are defective; physically arranging said chips in said memory according to chips that are identical as to which areas have defective cells anD which do not, so that chips in the same class are placed in the same relative position in said memory; and translating contiguous addresses presented to said memory so that cells in said chips containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 6
Independent Claim
143 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of addressable memory cells, which method utilizes partially defective chips comprising the steps of: sorting said chips into perfect, partially defective, and defective chips; sorting said partially defective chips into classes based upon which cells of the chips are defective; physically arranging said chips in said memory according to chips that are identical as to which areas have defective cells anD which do not, so that chips in the same class are placed in the same relative position in said memory; and translating contiguous addresses presented to said memory so that cells in said chips containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 7
Independent Claim
172 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of memory cells, which chips are placed on modules, which modules are placed in an array on a circuit card, one card for each bit position of a word in said memory, comprising the steps of: sorting said chips into perfect, partially defective, and defective chips; sorting said partially defective chips into classes based upon which cells of the chips are defective; physically arranging said chips on said modules by class according to chips that are identical as to which areas have defective cells and which do not, so that chips in the same class are placed in the same relative chip position on each module in the memory; and translating contiguous addresses presented to said memory so that word locations on the chips containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 8
Independent Claim
172 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of memory cells, which chips are placed on modules, which modules are placed in an array on a circuit card, one card for each bit position of a word in said memory, comprising the steps of: sorting said chips into perfect, partially defective, and defective chips; sorting said partially defective chips into classes based upon which cells of the chips are defective; physically arranging said chips on said modules by class according to chips that are identical as to which areas have defective cells and which do not, so that chips in the same class are placed in the same relative chip position on each module in the memory; and translating contiguous addresses presented to said memory so that word locations on the chips containing defects are logically placed in high order address positions which are outside the range of said contiguous addresses.
Claim 9
Independent Claim
133 words
The method of using perfect, partially defective and defective memory units in the manufacture of a memory of the type which is constructed of units containing a plurality of addressable memory cells, which method utilizes partially defective units comprising the steps of: sorting said units into classes based upon which areas of the units are not defective and which areas are defective; physically arranging said units in said memory according to units that are identical as to which areas are not defective so that units in the same class are placed in the same relative position in said memory; and providing means for translating contiguous addresses presented to said memory so that cells in said units containing defects are logically placed in address positions which are outside the range of said contiguous addresses.
Claim 10
Independent Claim
133 words
The method of using perfect, partially defective and defective memory units in the manufacture of a memory of the type which is constructed of units containing a plurality of addressable memory cells, which method utilizes partially defective units comprising the steps of: sorting said units into classes based upon which areas of the units are not defective and which areas are defective; physically arranging said units in said memory according to units that are identical as to which areas are not defective so that units in the same class are placed in the same relative position in said memory; and providing means for translating contiguous addresses presented to said memory so that cells in said units containing defects are logically placed in address positions which are outside the range of said contiguous addresses.
Claim 11
Independent Claim
134 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of addressable memory cells, which method utilizes partially defective chips comprising the steps of: sorting said chips into classes based upon which cells of the chips are not defective and which areas are defective; physically arranging said chips in said memory according to chips that are identical as to which cells are not defective so that chips in the same class are placed in the same relative position in said memory; and providing means for translating contiguous addresses presented to said memory so that cells in said chips containing defects are logically placed in address positions which are outside the range of said contiguous addresses.
Claim 12
Independent Claim
134 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of addressable memory cells, which method utilizes partially defective chips comprising the steps of: sorting said chips into classes based upon which cells of the chips are not defective and which areas are defective; physically arranging said chips in said memory according to chips that are identical as to which cells are not defective so that chips in the same class are placed in the same relative position in said memory; and providing means for translating contiguous addresses presented to said memory so that cells in said chips containing defects are logically placed in address positions which are outside the range of said contiguous addresses.
Claim 13
Independent Claim
163 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of memory cells, which chips are placed on modules, which modules are placed in an array on a circuit card, one card for each bit position of a word in said memory, comprising the steps of: sorting said chips into classes based upon which cells of the chips are not defective and which cells are defective; physically arranging said chips on said modules by class according to chips that are identical as to which cells are not defective so that chips in the same class are placed in the same relative chip position on each module in the memory; and providing means for translating contiguous addresses presented to said memory so that word locations on the chips containing defects are logically placed in address positions which are outside tHe range of said contiguous addresses.
Claim 14
Independent Claim
163 words
The method of using perfect, partially defective and defective memory units in the manufacture of a monolithic memory of the type which is constructed of chips containing a plurality of memory cells, which chips are placed on modules, which modules are placed in an array on a circuit card, one card for each bit position of a word in said memory, comprising the steps of: sorting said chips into classes based upon which cells of the chips are not defective and which cells are defective; physically arranging said chips on said modules by class according to chips that are identical as to which cells are not defective so that chips in the same class are placed in the same relative chip position on each module in the memory; and providing means for translating contiguous addresses presented to said memory so that word locations on the chips containing defects are logically placed in address positions which are outside tHe range of said contiguous addresses.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |